2 Pin Allocation Tables

Table 2-1. 8-Pin Allocation Table
I/O	8-Pin PDIP SOIC	ADC	Reference	Comparator	ZCD	Timers	CCP	16-Bit PWM	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	7	ANNA0 ANPA0	DAC1OUT1	C1IN0+	—	T3CKI⁽¹⁾ T3G⁽¹⁾ T4IN⁽¹⁾	—	PWMIN0⁽¹⁾ PWMIN1⁽¹⁾ PWM2ERS⁽¹⁾	—	CLCIN3⁽¹⁾	SCL2^(1,3) SCK2^(1,3) SDA2^(1,3) SDI2^(1,3) SS2⁽¹⁾	CK1^(1,3) CK2^(1,3)	IOCA0	—	ICSPDAT ICDDAT
RA1	6	ANNA1 ANPA1	V_REF+ (ADC) DAC1REF0+ DAC2REF0+	C1IN0-	—	—	—	—	—	CLCIN2⁽¹⁾	SCL1^(1,3) SCK1^(1,3)	RX1⁽¹⁾ DT1^(1,3) RX2⁽¹⁾ DT2^(1,3)	IOCA1	—	ICSPCLK ICDCLK
RA2	5	ANNA2 ANPA2	DAC1REF0- DAC2REF0-	—	ZCD1	T0CKI⁽¹⁾	—	—	CWG1⁽¹⁾	—	SDA1^(1,3) SDI1^(1,3)	—	IOCA2	INT⁽¹⁾	—
RA3	4	—	—	—	—	—	—	—	—	CLCIN0 ⁽¹⁾	SS1⁽¹⁾	—	IOCA3	—	MCLR V_PP
RA4	3	ANNA4 ANPA4	—	C1IN1-	—	T1G⁽¹⁾	—	—	—	—	—	—	IOCA4	—	CLKOUT OSC2 SOSCO
RA5	2	ANNA5 ANPA5 ADACT⁽¹⁾	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	CCP1⁽¹⁾ CCP2⁽¹⁾	PWM1ERS⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	IOCA5	—	CLKIN OSC1 SOSCI
V_DD	1	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	8	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	ADGRDA ADGRDB	—	CMP1	—	TMR0	CCP1 CCP2	PWM11 PWM12 PWM21 PWM22	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers.

Table 2-2. 14/16-Pin Allocation Table
I/O	14-Pin PDIP SOIC TSSOP	16-Pin VQFN	ADC	Reference	Comparator	ZCD	Timers	CCP	16-Bit PWM	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	13	12	ANNA0 ANPA0	DAC1OUT1	C1IN0+	—	—	—	—	—	—	SS2⁽¹⁾	—	IOCA0	—	ICSPDAT ICDDAT
RA1	12	11	ANNA1 ANPA1	V_REF+(ADC) DAC1REF0+ DAC2REF0+	C1IN0- C2IN0-	—	—	—	—	—	—	—	—	IOCA1	—	ICSPCLK ICDCLK
RA2	11	10	ANNA2 ANPA2	DAC1OUT2 DAC1REF0- DAC2REF0-	—	ZCD1	T0CKI⁽¹⁾	—	—	CWG1⁽¹⁾	—	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	3	—	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	2	ANNA4 ANPA4	—	—	—	T1G⁽¹⁾	—	—	—	—	—	—	IOCA4	—	CLKOUT OSC2 SOSCO
RA5	2	1	ANNA5 ANPA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	PWM1ERS⁽¹⁾	—	CLCIN3⁽¹⁾	—	—	IOCA5	—	CLKIN OSC1 SOSCI
RC0	10	9	ANNC0 ANPC0	—	C2IN0+	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	CK2^(1,3)	IOCC0	—	—
RC1	9	8	ANNC1 ANPC1	—	C1IN1- C2IN1-	—	T4IN⁽¹⁾	—	PWM2ERS⁽¹⁾	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	RX2⁽¹⁾ DT2^(1,3)	IOCC1	—	—
RC2	8	7	ANNC2 ANPC2 ADACT⁽¹⁾	—	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	IOCC2	—	—
RC3	7	6	ANNC3 ANPC3	—	C1IN3- C2IN3-	—	—	CCP2⁽¹⁾	PWMIN1⁽¹⁾	—	CLCIN0⁽¹⁾	SS1⁽¹⁾	—	IOCC3	—	—
RC4	6	5	ANNC4 ANPC4	—	—	—	T3G⁽¹⁾	—	—	—	CLCIN1⁽¹⁾	SCK2^(1,3,4) SCL2^(1,3,4)	CK1^(1,3)	IOCC4	—	—
RC5	5	4	ANNC5 ANPC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	PWMIN0⁽¹⁾	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	RX1⁽¹⁾ DT1^(1,3)	IOCC5	—	—
V_DD	1	16	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	14	13	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1 CMP2	—	TMR0	CCP1 CCP2	PWM11 PWM12 PWM21 PWM22	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table 2-3. 20-Pin Allocation Table
I/O	20-Pin PDIP SOIC SSOP	20-Pin VQFN	ADC	Reference	Comparator	ZCD	Timers	CCP	16-Bit PWM	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	19	16	ANNA0 ANPA0	DAC1OUT1	C1IN0+	—	—	—	—	—	—	—	—	IOCA0	—	ICSPDAT ICDDAT
RA1	18	15	ANNA1 ANPA1	V_REF+(ADC) DAC1REF0+ DAC2REF0+	C1IN0- C2IN0-	—	—	—	—	—	—	SS2⁽¹⁾	—	IOCA1	—	ICSPCLK ICDCLK
RA2	17	14	ANNA2 ANPA2	DAC1OUT2 DAC1REF0- DAC2REF0-	—	ZCD1	T0CKI⁽¹⁾	—	—	CWG1⁽¹⁾	CLCIN0⁽¹⁾	—	—	IOCA2	INT⁽¹⁾	—
RA3	4	1	—	—	—	—	—	—	—	—	—	—	—	IOCA3	—	MCLR V_PP
RA4	3	20	ANNA4 ANPA4	—	—	—	T1G⁽¹⁾	—	—	—	—	—	—	IOCA4	—	CLKOUT OSC2 SOSCO
RA5	2	19	ANNA5 ANPA5	—	—	—	T1CKI⁽¹⁾ T2IN⁽¹⁾	—	PWM1ERS⁽¹⁾	—	—	—	—	IOCA5	—	CLKIN OSC1 SOSCI
RB4	13	10	ANNB4 ANPB4	—	—	—	—	—	—	—	CLCIN2⁽¹⁾	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCB4	—	—
RB5	12	9	ANNB5 ANPB5	—	—	—	—	—	—	—	CLCIN3⁽¹⁾	SDA2^(1,3,4) SDI2^(1,3,4)	RX1⁽¹⁾ DT1^(1,3)	IOCB5	—	—
RB6	11	8	ANNB6 ANPB6	—	—	—	—	—	—	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCB6	—	—
RB7	10	7	ANNB7 ANPB7	—	—	—	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	CK1^(1,3)	IOCB7	—	—
RC0	16	13	ANNC0 ANPC0	—	C2IN0+	—	—	—	—	—	—	—	CK2^(1,3)	IOCC0	—	—
RC1	15	12	ANNC1 ANPC1	—	C1IN1- C2IN1-	—	T4IN⁽¹⁾	—	PWM2ERS⁽¹⁾	—	—	—	RX2⁽¹⁾ DT2^(1,3)	IOCC1	—	—
RC2	14	11	ANNC2 ANPC2 ADACT⁽¹⁾	—	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	IOCC2	—	—
RC3	7	4	ANNC3 ANPC3	—	C1IN3- C2IN3-	—	—	CCP2⁽¹⁾	PWMIN1⁽¹⁾	—	CLCIN1⁽¹⁾	—	—	IOCC3	—	—
RC4	6	3	ANNC4 ANPC4	—	—	—	T3G⁽¹⁾	—	—	—	—	—	—	IOCC4	—	—
RC5	5	2	ANNC5 ANPC5	—	—	—	T3CKI⁽¹⁾	CCP1⁽¹⁾	PWMIN0⁽¹⁾	—	—	—	—	IOCC5	—	—
RC6	8	5	ANNC6 ANPC6	—	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCC6	—	—
RC7	9	6	ANNC7 ANPC7	—	—	—	—	—	—	—	—	—	—	IOCC7	—	—
V_DD	1	18	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	20	17	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1 CMP2	—	TMR0	CCP1 CCP2	PWM11 PWM12 PWM21 PWM22	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to any PORTx pin. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table 2-4. 28-Pin Allocation Table
I/O	28-Pin SPDIP SOIC SSOP	28-Pin VQFN	ADC	Reference	Comparator	ZCD	Timers	CCP	16-Bit PWM	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	2	27	ANPA0	—	C1IN0- C2IN0-	—	—	—	—	—	CLCIN0⁽¹⁾	—	—	IOCA0	—	—
RA1	3	28	ANNA1 ANPA1	—	C1IN1- C2IN1-	—	—	—	—	—	CLCIN1⁽¹⁾	—	—	IOCA1	—	—
RA2	4	1	ANPA2	DAC1OUT1 DAC1REF0-	C1IN0+ C2IN0+	—	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	2	ANNA3 ANPA3	DAC1REF0+ V_REF+ (ADC)	C1IN1+	—	—	—	—	—	—	—	—	IOCA3	—	—
RA4	6	3	ANPA4	—	—	—	T0CKI⁽¹⁾	—	—	—	—	—	—	IOCA4	—	—
RA5	7	4	ANNA5 ANPA5	—	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCA5	—	—
RA6	10	7	ANNA6 ANPA6	—	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT OSC2
RA7	9	6	ANPA7	—	—	—	—	—	—	—	—	—	—	IOCA7	—	CLKIN OSC1
RB0	21	18	ANNB0 ANPB0	DAC2REF0+	C2IN1+	ZCD1	—	—	—	CWG1⁽¹⁾	—	SS2⁽¹⁾	—	IOCB0	INT⁽¹⁾	—
RB1	22	19	ANPB1	—	C1IN3- C2IN3-	—	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	—	IOCB1	—	—
RB2	23	20	ANNB2 ANPB2	—	—	—	—	—	—	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	—	IOCB2	—	—
RB3	24	21	ANPB3	—	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	IOCB3	—	—
RB4	25	22	ANNB4 ANPB4 ADACT⁽¹⁾	—	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	26	23	ANPB5	DAC2REF0-	—	—	T1G⁽¹⁾	—	—	—	—	—	—	IOCB5	—	—
RB6	27	24	ANNB6 ANPB6	—	—	—	—	—	—	—	CLCIN2⁽¹⁾	—	CK2^(1,3)	IOCB6	—	ICSPCLK ICDCLK
RB7	28	25	ANPB7	DAC1OUT2	—	—	T6IN⁽¹⁾	—	PWM3ERS⁽¹⁾	—	CLCIN3⁽¹⁾	—	RX2⁽¹⁾ DT2^(1,3)	IOCB7	—	ICSPDAT ICDDAT
RC0	11	8	ANPC0	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾	—	—	—	—	—	—	IOCC0	—	SOSCO
RC1	12	9	ANNC1 ANPC1	—	—	—	—	CCP2⁽¹⁾	PWMIN1⁽¹⁾	—	—	—	—	IOCC1	—	—
RC2	13	10	ANPC2	—	—	—	—	CCP1⁽¹⁾	PWMIN0⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3	14	11	ANNC3 ANPC3	—	—	—	T2IN⁽¹⁾	—	PWM1ERS⁽¹⁾ PWM4ERS⁽¹⁾	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCC3	—	—
RC4	15	12	ANPC4	—	—	—	—	—	—	—	—	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCC4	—	—
RC5	16	13	ANPC5	—	—	—	T4IN⁽¹⁾	—	PWM2ERS⁽¹⁾	—	—	—	—	IOCC5	—	—
RC6	17	14	ANNC6 ANPC6	—	—	—	—	—	—	—	—	—	CK1^(1,3)	IOCC6	—	—
RC7	18	15	ANPC7	—	—	—	—	—	—	—	—	—	RX1⁽¹⁾ DT1^(1,3)	IOCC7	—	—
RE3	1	26	—	—	—	—	—	—	—	—	—	—	—	IOCE3	—	MCLR V_PP
V_DD	20	17	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	8 19	5 16	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	ADGRDA ADGRDB	—	CMP1 CMP2	—	TMR0	CCP1 CCP2	PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 PWM41 PWM42	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.

Table 2-5. 40/44-Pin Allocation Table
I/O	40-Pin PDIP	40-Pin VQFN	44-Pin TQFP	ADC	Reference	Comparator	ZCD	Timers	CCP	16-Bit PWM	CWG	CLC	MSSP	EUSART	IOC	Interrupt	Basic
RA0	2	17	19	ANPA0	—	C1IN0- C2IN0-	—	—	—	—	—	CLCIN0⁽¹⁾	—	—	IOCA0	—	—
RA1	3	18	20	ANNA1 ANPA1	—	C1IN1- C2IN1-	—	—	—	—	—	CLCIN1⁽¹⁾	—	—	IOCA1	—	—
RA2	4	19	21	ANPA2	DAC1OUT1 DAC1REF0-	C1IN0+ C2IN0+	—	—	—	—	—	—	—	—	IOCA2	—	—
RA3	5	20	22	ANNA3 ANPA3	DAC1REF0+ V_REF+ (ADC)	C1IN1+	—	—	—	—	—	—	—	—	IOCA3	—	—
RA4	6	21	23	ANPA4	—	—	—	T0CKI⁽¹⁾	—	—	—	—	—	—	IOCA4	—	—
RA5	7	22	24	ANNA5 ANPA5	—	—	—	—	—	—	—	—	SS1⁽¹⁾	—	IOCA5	—	—
RA6	14	29	31	ANNA6 ANPA6	—	—	—	—	—	—	—	—	—	—	IOCA6	—	CLKOUT OSC2
RA7	13	28	30	ANPA7	—	—	—	—	—	—	—	—	—	—	IOCA7	—	CLKIN OSC1
RB0	33	8	8	ANNB0 ANPB0	DAC2REF0+	C2IN1+	ZCD1	—	—	—	CWG1⁽¹⁾	—	SS2⁽¹⁾	—	IOCB0	INT⁽¹⁾	—
RB1	34	9	9	ANPB1	—	C1IN3- C2IN3-	—	—	—	—	—	—	SCL2^(1,3,4) SCK2^(1,3,4)	—	IOCB1	—	—
RB2	35	10	10	ANNB2 ANPB2	—	—	—	—	—	—	—	—	SDA2^(1,3,4) SDI2^(1,3,4)	—	IOCB2	—	—
RB3	36	11	11	ANPB3	—	C1IN2- C2IN2-	—	—	—	—	—	—	—	—	IOCB3	—	—
RB4	37	12	14	ANNB4 ANPB4 ADACT⁽¹⁾	—	—	—	—	—	—	—	—	—	—	IOCB4	—	—
RB5	38	13	15	ANPB5	DAC2REF0-	—	—	T1G⁽¹⁾	—	—	—	—	—	—	IOCB5	—	—
RB6	39	14	16	ANNB6 ANPB6	—	—	—	—	—	—	—	CLCIN2⁽¹⁾	—	CK2^(1,3)	IOCB6	—	ICSPCLK ICDCLK
RB7	40	15	17	ANPB7	DAC1OUT2	—	—	T6IN⁽¹⁾	—	PWM3ERS⁽¹⁾	—	CLCIN3⁽¹⁾	—	RX2⁽¹⁾ DT2^(1,3)	IOCB7	—	ICSPDAT ICDDAT
RC0	15	30	32	ANPC0	—	—	—	T1CKI⁽¹⁾ T3CKI⁽¹⁾ T3G⁽¹⁾	—	—	—	—	—	—	IOCC0	—	SOSCO
RC1	16	31	35	ANNC1 ANPC1	—	—	—	—	CCP2⁽¹⁾	PWMIN1⁽¹⁾	—	—	—	—	IOCC1	—	—
RC2	17	32	36	ANPC2	—	—	—	—	CCP1⁽¹⁾	PWMIN0⁽¹⁾	—	—	—	—	IOCC2	—	—
RC3	18	33	37	ANNC3 ANPC3	—	—	—	T2IN⁽¹⁾	—	PWM1ERS⁽¹⁾ PWM4ERS⁽¹⁾	—	—	SCL1^(1,3,4) SCK1^(1,3,4)	—	IOCC3	—	—
RC4	23	38	42	ANPC4	—	—	—	—	—	—	—	—	SDA1^(1,3,4) SDI1^(1,3,4)	—	IOCC4	—	—
RC5	24	39	43	ANPC5	—	—	—	T4IN⁽¹⁾	—	PWM2ERS⁽¹⁾	—	—	—	—	IOCC5	—	—
RC6	25	40	44	ANNC6 ANPC6	—	—	—	—	—	—	—	—	—	CK1^(1,3)	IOCC6	—	—
RC7	26	1	1	ANPC7	—	—	—	—	—	—	—	—	—	RX1⁽¹⁾ DT1^(1,3)	IOCC7	—	—
RD0	19	34	38	ANPD0	—	—	—	—	—	—	—	—	—	—	—	—	—
RD1	20	35	39	ANPD1	—	—	—	—	—	—	—	—	—	—	—	—	—
RD2	21	36	40	ANND2 ANPD2	—	—	—	—	—	—	—	—	—	—	—	—	—
RD3	22	37	41	ANND3 ANPD3	—	—	—	—	—	—	—	—	—	—	—	—	—
RD4	27	2	2	ANPD4	—	—	—	—	—	—	—	—	—	—	—	—	—
RD5	28	3	3	ANND5 ANPD5	—	—	—	—	—	—	—	—	—	—	—	—	—
RD6	29	4	4	ANPD6	—	—	—	—	—	—	—	—	—	—	—	—	—
RD7	30	5	5	ANND7 ANPD7	—	—	—	—	—	—	—	—	—	—	—	—	—
RE0	8	23	25	ANPE0	—	—	—	—	—	—	—	—	—	—	—	—	—
RE1	9	24	26	ANNE1 ANPE1	—	—	—	—	—	—	—	—	—	—	—	—	—
RE2	10	25	27	ANPE2	—	—	—	—	—	—	—	—	—	—	—	—	—
RE3	1	16	18	—	—	—	—	—	—	—	—	—	—	—	IOCE3	—	MCLR V_PP
V_DD	11 32	7 26	7 28	—	—	—	—	—	—	—	—	—	—	—	—	—	V_DD
V_SS	12 31	6 27	6 29	—	—	—	—	—	—	—	—	—	—	—	—	—	V_SS
OUT⁽²⁾	—	—	—	ADGRDA ADGRDB	—	CMP1 CMP2	—	TMR0	CCP1 CCP2	PWM11 PWM12 PWM21 PWM22 PWM31 PWM32 PWM41 PWM42	CWG1A CWG1B CWG1C CWG1D	CLC1OUT CLC2OUT CLC3OUT CLC4OUT	SCL1 SCK1 SDA1 SDO1 SCL2 SCK2 SDA2 SDO2	TX1 DT1 CK1 TX2 DT2 CK2	—	—	—
Note: This is a PPS remappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. Refer to the PPS input table in the device data sheet for details on which PORT pins may be used for this signal. All output signals shown in this row are PPS remappable. This is a bidirectional signal. For normal operation, user software must map this signal to the same pin via the PPS input and PPS output registers. These pins can be configured for I²C or SMBus logic levels via the RxyI2C registers. The SCL1/SDA1 signals may be assigned to these pins for expected operation. PPS assignments of these signals to other pins will operate; however, the logic levels will be standard TTL/ST as selected by the INLVL register.