1.2 External Interrupt Sensing

External interrupts can be sensed and registered either synchronously or asynchronously. Synchronous sensing requires I/O clock whereas asynchronous sensing does not requires I/O clock. This implies that the interrupts that are detected asynchronously can be used for waking the device from sleep modes other than idle mode because the I/O clock is halted in all sleep modes except idle mode.

The sense configuration for external interrupts and pin change interrupts for Atmel ATtiny88 is given in table below. For device specific sense configuration, refer to the respective datasheet.

Table 1-2. External Interrupts Sense Configuration
Program addressInterrupt sourceSensing
$001INT0Asynchronous (level)
Synchronous (edges)
$002INT1Asynchronous (level)
Synchronous (edges)
$003PCINT0Asynchronous
$004PCINT1Asynchronous
$005PCINT2Asynchronous
$006PCINT3Asynchronous

From the table above all the pin change interrupts are detected asynchronously. Other interrupts (INT0 and INT1) can be triggered by sensing the rising or falling edges or low level on the corresponding interrupt pins. The type of sensing (edge or level) for each of the INTn (n = 0 and 1 for ATtiny88) interrupts is software configurable using two Interrupt Sense Control (ISC) bits per interrupt. This is provided in the following table.

Table 1-3. External Interrupts Individual Sense Configuration
ISCn1ISCn0Description
00The low level of INTn generates an interrupt request
01Any edge of INTn generates an interrupt request
10The falling edge of INTn generates an interrupt request
11The rising edge of INTn generates an interrupt request
Note: PCINT27:0 does not have sense configuration options. This means that the interrupt will be generated whenever there is a logic change in the pin, that is, from high to low transition and low to high transition.