5.3.3.1 Reset and Discovery Response Timing

Table 5-4. Reset and Discovery Response TimingUnless otherwise indicated, these values are applicable over the specified operating range from TA = -40℃ to +105℃, VCC = +1.65V to +5.5V, CL = 100 pF.
Parameter and Condition(1) Sym. Min. Max. Units
Reset Low Time, Device in Inactive State(4) tRESET 96 µs
Reset Recovery Time(4, 6) Clock Divider = 1x tRRT 1000 µs
Clock Divider = 2x 1200 µs
Clock Divider = 4x 1800 µs
Discovery Response Request(4) tDRR 1 2 – tPUP(2) µs
Discovery Response Acknowledge Time(5) tDACK 2 6(3) µs
Host Strobe Discovery Response Time(4) tMSDR tRD + tPUP(2) 2 µs
SI/O High Time for Start/Stop Condition(4) tHTSS 150 µs
Note:
  1. AC measurement conditions for the table above:
    • All parameters are production tested unless otherwise noted.
    • Loading capacitance on SI/O: 100 pF
    • VPUP: Applied at minimum and maximum VCC
  2. tPUP is the time required to be pulled up from VIL to VIH when the SI/O line is released. This value is application-specific and is a function of the loading capacitance on the SI/O line as well as the RPUP chosen.
  3. Microchip’s AT21CS11 supports a maximum of 24 µs and a minimum of 8 µs.
  4. The host system must ensure the parameter timing values are met.
  5. The ECC204-TFLXAUTH ensures by design this timing parameter is met.
  6. Parameter is ensured through characterization but is not production tested.