12.4 Operation

Interrupts are disabled upon any device Reset. They are enabled by setting the following bits:
  • GIE bit
  • PEIE bit (if the Interrupt Enable bit of the interrupt event is contained in the PIE registers)
  • Interrupt Enable bit(s) for the specific interrupt event(s)

The PIR registers record individual interrupts via interrupt flag bits. Interrupt flag bits will be set, regardless of the status of the GIE, PEIE and individual interrupt enable bits.

The following events happen when an interrupt event occurs while the GIE bit is set:
  • Current prefetched instruction is flushed
  • GIE bit is cleared
  • Current Program Counter (PC) is pushed onto the stack
  • Critical registers are automatically saved to the shadow registers (see Automatic Context Saving)
  • PC is loaded with the interrupt vector 0004h

The firmware within the Interrupt Service Routine (ISR) may determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector.

The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit.

For additional information on a specific interrupts operation, refer to its peripheral section.
Important:
  1. Individual interrupt flag bits are set, regardless of the state of any other enable bits.
  2. All interrupts will be ignored while the GIE bit is cleared. Any interrupt occurring while the GIE bit is clear will be serviced when the GIE bit is set again.