Writes to PORTx are actually
written to the corresponding LATx register. Reads from PORTx register return
actual I/O pin values.
The PORT bit associated with the
MCLR pin is read-only and will read
‘1’ when the MCLR function is enabled
(LVP = 1 or (LVP = 0 and MCLRE =
1))
Refer to the “Pin Allocation
Table” for details about MCLR pin and pin
availability per port
Unimplemented bits will read back
as ‘0’
Name:
PORTx
Bit
7
6
5
4
3
2
1
0
Rx7
Rx6
Rx5
Rx4
Rx3
Rx2
Rx1
Rx0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
x
x
x
x
x
x
x
x
Bits 0, 1, 2, 3, 4, 5, 6, 7 – Rxn Port I/O Value
Reset States:
POR/BOR = xxxxxxxx
All Other Resets = uuuuuuuu
Value
Description
1
PORT pin is ≥ VIH
0
PORT pin is ≤ VIL
Writes to PORTx are actually
written to the corresponding LATx register. Reads from PORTx register return
actual I/O pin values.
The PORT bit associated with the
MCLR pin is read-only and will read
‘1’ when the MCLR function is enabled
(LVP = 1 or (LVP = 0 and MCLRE =
1))
Refer to the “Pin Allocation
Table” for details about MCLR pin and pin
availability per port
Unimplemented bits will read back
as ‘0’
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
