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11.13.35 IPR8
Peripheral Interrupt
Priority Register 8| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | | I3C1RIP | I3C1EIP | I3C1IP | I3C1TXIP | I3C1RXIP | |
| Access | | | | R/W | R/W | R/W | R/W | R/W | |
| Reset | | | | 1 | 1 | 1 | 1 | 1 | |
Bit 4 – I3C1RIP I3C1 Reset Interrupt Priority
| Value | Description |
|---|
| 1 |
High Priority |
| 0 |
Low Priority |
Bit 3 – I3C1EIP I3C1 Error
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 2 – I3C1IP I3C1 General
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 1 – I3C1TXIP I3C1 Transmit
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
Bit 0 – I3C1RXIP I3C1 Receive
Interrupt Priority
| Value | Description |
|---|
| 1 |
High
Priority |
| 0 |
Low
Priority |
