20.2 Features

  • Data Transfer From:
    • Peripheral-to-peripheral
    • Peripheral-to-memory
    • Memory-to-peripheral
    • Memory-to-memory
  • Transfer Trigger Sources:
    • Software
    • Events from Event System
    • Dedicated requests from peripherals
  • SRAM-based Transfer Descriptors:
    • Single transfer using one descriptor
    • Multi-buffer or Circular Buffer modes by linking multiple descriptors
  • Up to 12 Channels:
    • Enable 12 independent transfers
    • Automatic descriptor fetch for each channel
    • Suspend/resume operation support for each channel
  • Flexible Arbitration Scheme:
    • 4 configurable priority levels for each channel
    • Fixed or round-robin priority scheme within each priority level
  • From 1 to 256KB Data Transfer in a Single Block Transfer
  • Multiple Addressing Modes:
    • Static
    • Configurable increment scheme
  • Optional Interrupt Generation:
    • On block transfer complete
    • On error detection
    • On channel suspend
  • 4 Event Inputs:
    • One event input for each of the 4 least significant DMA channels
    • Can be selected to trigger normal transfers, periodic transfers or conditional transfers
    • Can be selected to suspend or resume channel operation
  • 4 Event Outputs:
    • One output event for each of the 4 least significant DMA channels
    • Selectable generation on AHB, block, or transaction transfer complete
  • Error Management Supported by Write-back Function:
    • Dedicated write-back memory section for each channel to store ongoing descriptor transfer
  • CRC Polynomial Software Selectable to:
    • CRC-16 (CRC-CCITT)
    • CRC-32 (IEEE® 802.3)