15.8.3 Generic Clock Control

Name: CLKCTRL
Offset: 0x2
Reset: 0x0000
Property: Write-Protected

Bit 15141312111098 
 WRTLOCKCLKEN  GEN[3:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
   ID[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 15 – WRTLOCK Write Lock

When this bit is written, it will lock from further writes the generic clock pointed to by CLKCTRL.ID, the generic clock generator pointed to in CLKCTRL.GEN and the division factor used in the generic clock generator. It can only be unlocked by a Power Reset.

One exception to this is generic clock generator 0, which cannot be locked.

ValueDescription
0The generic clock and the associated generic clock generator and division factor are not locked
1The generic clock and the associated generic clock generator and division factor are locked

Bit 14 – CLKEN Clock Enable

This bit is used to enable and disable a generic clock.

ValueDescription
0The generic clock is disabled
1The generic clock is enabled

Bits 11:8 – GEN[3:0] Generic Clock Generator

These bits define the Generic Clock Generator which will be associated with the peripheral GCLK clock defined in the CLKCTRL.ID.

Table 15-2. Generic Clock Generator
GEN[3:0]NameDescription
0x0GCLKGEN0Generic clock generator 0
0x1GCLKGEN1Generic clock generator 1
0x2GCLKGEN2Generic clock generator 2
0x3GCLKGEN3Generic clock generator 3
0x4GCLKGEN4Generic clock generator 4
0x5GCLKGEN5Generic clock generator 5
0x6GCLKGEN6Generic clock generator 6
0x7GCLKGEN7Generic clock generator 7
0x8GCLKGEN8Generic clock generator 8
0x9-0xF-Reserved

Bits 5:0 – ID[5:0] Generic Clock Selection ID

These bits select the peripheral GCLK clock which will be associated with the Generic Clock Generator defined in the CLKCTRL.GEN. The third table below provides the ID number for each possible peripheral GCLK clock..

A Power Reset will reset the CLKCTRL register for all IDs, including the RTC. If the WRTLOCK bit of the corresponding ID is zero and the ID is not the RTC, a user Reset will reset the CLKCTRL register for this ID.

After a Power Reset, the Reset value of the CLKCTRL register versus module instance is as shown in the next table.

Table 15-3. CLKCTRL Value after Power Reset for each Peripheral GCLK clock ID
Module InstanceReset Value after Power Reset
CLKCTRL.GENCLKCTRL.CLKENCLKCTRL.WRTLOCK
RTC (ID = 0x04)0x000x000x00
WDT (ID = 0x03)0x020x01 if WDT Enable bit in NVM
User Row written to one
0x00 if WDT Enable bit in NVM
User Row written to zero0x01 if WDT Always-On bit in
NVM User Row written to one
0x00 if WDT Always-On bit in
NVM User Row written to zero
Others0x000x000x00

After a user Reset, the Reset value of the CLKCTRL register versus module instance is as shown in the table below.

Table 15-4. CLKCTRL Value after User Reset for each Peripheral GCLK clock ID
Module InstanceReset Value after a User Reset
CLKCTRL.GENCLCTRL.CLKENCLKCTRL.WRTLOCK
RTC (ID = 0x04)0x00 if WRTLOCK=0 and
CLKEN=0
No change if WRTLOCK=1
or CLKEN=10x00 if WRTLOCK=0 and CLKEN=0
No change if WRTLOCK=1 or CLKEN=1No change
WDT (ID = 0x03)0x02 if WRTLOCK=0
No change if WRTLOCK=1If WRTLOCK=0
0x01 if WDT Enable bit in NVM User
Row written to one
0x00 if WDT Enable bit in NVM User
Row written to zero
If WRTLOCK=1 no changeNo change
Others0x00 if WRTLOCK=0
No change if WRTLOCK=10x00 if WRTLOCK=0
No change if WRTLOCK=1No change
ValueNameDescription
0x00GCLK_DFLL48M_REFDFLL48M Reference
0x01GCLK_DPLLFDPLL96M input clock source for reference
0x02GCLK_DPLL_32KFDPLL96M 32 kHz clock for FDPLL96M internal lock timer
0x03GCLK_WDTWDT
0x04GCLK_RTCRTC
0x05GCLK_EICEIC
0x06GCLK_USBUSB
0x07GCLK_EVSYS_CHANNEL_0EVSYS_CHANNEL_0
0x08GCLK_EVSYS_CHANNEL_1EVSYS_CHANNEL_1
0x09GCLK_EVSYS_CHANNEL_2EVSYS_CHANNEL_2
0x0AGCLK_EVSYS_CHANNEL_3EVSYS_CHANNEL_3
0x0BGCLK_EVSYS_CHANNEL_4EVSYS_CHANNEL_4
0x0CGCLK_EVSYS_CHANNEL_5EVSYS_CHANNEL_5
0x0DGCLK_EVSYS_CHANNEL_6EVSYS_CHANNEL_6
0x0EGCLK_EVSYS_CHANNEL_7EVSYS_CHANNEL_7
0x0FGCLK_EVSYS_CHANNEL_8EVSYS_CHANNEL_8
0x10GCLK_EVSYS_CHANNEL_9EVSYS_CHANNEL_9
0x11GCLK_EVSYS_CHANNEL_10EVSYS_CHANNEL_10
0x12GCLK_EVSYS_CHANNEL_11EVSYS_CHANNEL_11
0x13GCLK_SERCOMx_SLOWSERCOMx_SLOW
0x14GCLK_SERCOM0_CORESERCOM0_CORE
0x15GCLK_SERCOM1_CORESERCOM1_CORE
0x16GCLK_SERCOM2_CORESERCOM2_CORE
0x17GCLK_SERCOM3_CORESERCOM3_CORE
0x18GCLK_SERCOM4_CORESERCOM4_CORE
0x19GCLK_SERCOM5_CORESERCOM5_CORE
0x1AGCLK_TCC0, GCLK_TCC1TCC0,TCC1
0x1BGCLK_TCC2, GCLK_TC3TCC2,TC3
0x1CGCLK_TC4, GCLK_TC5TC4,TC5
0x1DGCLK_TC6, GCLK_TC7TC6,TC7
0x1EGCLK_ADCADC
0x1FGCLK_AC_DIG, GCLK_AC1_DIGAC_DIG, AC1_DIG
0x20GCLK_AC_ANA, GCLK_AC1_ANAAC_ANA, AC1_ANA
0x21GCLK_DACDAC
0x22GCLK_PTCPTC
0x23GCLK_I2S_0I2S_0
0x24GCLK_I2S_1I2S_1
0x25GCLK_TCC3TCC3
0x26-0x3F-Reserved