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Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog and PWM SAM D21/DA1 Family
Low-Power, 32-bit Cortex-M0+ MCU with Advanced Analog and PWM SAM D21/DA1 Family
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ATSAMD21E15 ATSAMD21E15L ATSAMD21E16 ATSAMD21E16L ATSAMD21E17 ATSAMD21E18 ATSAMD21G15 ATSAMD21G16 ATSAMD21G16L ATSAMD21G17 ATSAMD21G18 ATSAMD21J15 ATSAMD21J16 ATSAMD21J17 ATSAMD21J18
  1. Home
  2. 28 SERCOM I2C – Inter-Integrated Circuit
  3. 28.6 Functional Description
  4. 28.6.2 Basic Operation
  5. 28.6.2.4 I2C Host Operation
  6. 28.6.2.4.1 Host Clock Generation

SAM D21/DA1 Family

  • Features
  • 1 Description
  • 2 Configuration Summary
  • 3 SAM D21 Ordering Information(1)
  • 4 Block Diagram
  • 5 Pinout
  • 6 Signal Descriptions List
  • 7 I/O Multiplexing and Considerations
  • 8 Power Supply and Start-Up Considerations
  • 9 Product Mapping
  • 10 Memories
  • 11 Processor And Architecture
  • 12 Peripherals Configuration Summary
  • 13 DSU - Device Service Unit
  • 14 Clock System
  • 15 GCLK - Generic Clock Controller

  • 16 PM – Power Manager
  • 17 SYSCTRL – System Controller
  • 18 WDT – Watchdog Timer
  • 19 RTC – Real-Time Counter
  • 20 DMAC – Direct Memory Access Controller
  • 21 EIC – External Interrupt Controller
  • 22 Nonvolatile Memory Controller (NVMCTRL)
  • 23 PORT - I/O Pin Controller
  • 24 EVSYS – Event System
  • 25 SERCOM – Serial Communication Interface
  • 26 SERCOM USART
  • 27 SERCOM SPI – SERCOM Serial Peripheral Interface
  • 28 SERCOM I2C – Inter-Integrated Circuit
    • 28.1 Overview
    • 28.2 Features
    • 28.3 Block Diagram
    • 28.4 Signal Description
    • 28.5 Product Dependencies
    • 28.6 Functional Description
      • 28.6.1 Principle of Operation
      • 28.6.2 Basic Operation
        • 28.6.2.1 Initialization
        • 28.6.2.2 Enabling, Disabling, and Resetting
        • 28.6.2.3 I2C Bus State Logic
        • 28.6.2.4 I2C Host Operation
          • 28.6.2.4.1 Host Clock Generation
            • 28.6.2.4.1.1 Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus)
            • 28.6.2.4.1.2 Host Clock Generation (High-Speed Mode)
          • 28.6.2.4.2 Transmitting Address Packets
          • 28.6.2.4.3 Transmitting Data Packets
          • 28.6.2.4.4 Receiving Data Packets (SCLSM=0)
          • 28.6.2.4.5 Receiving Data Packets (SCLSM=1)
          • 28.6.2.4.6 High-Speed Mode
          • 28.6.2.4.7 10-Bit Addressing
        • 28.6.2.5 I2C Client Operation
      • 28.6.3 Additional Features
      • 28.6.4 DMA, Interrupts and Events
      • 28.6.5 Sleep Mode Operation
      • 28.6.6 Synchronization
    • 28.7 Register Summary - I2C Client
    • 28.8 Register Description - I2C Client
    • 28.9 Register Summary - I2C Host
    • 28.10 Register Description - I2C Host
  • 29 I2S - Inter-IC Sound Controller
  • 30 TC – Timer/Counter
  • 31 TCC – Timer/Counter for Control Applications
  • 32 USB – Universal Serial Bus
  • 33 ADC – Analog-to-Digital Converter
  • 34 AC – Analog Comparators
  • 35 DAC – Digital-to-Analog Converter
  • 36 Peripheral Touch Controller (PTC)
  • 37 Electrical Characteristics at 85℃
  • 38 Electrical Characteristics at 105°C
  • 39 Electrical Characteristics at 125°C
  • 40 AEC-Q100 125°C Specifications
  • 41 SAM DA1 Electrical Characteristics
  • 42 Appendix A
  • 43 Appendix B
  • 44 Packaging Information
  • 45 Schematic Checklist
  • 46 Conventions
  • 47 Acronyms and Abbreviations
  • 48 Data Sheet Revision History
  • The Microchip Web Site
  • Customer Change Notification Service
  • Customer Support
  • Product Identification System
  • Microchip Devices Code Protection Feature
  • Legal Notice
  • Trademarks
  • Quality Management System Certified by DNV
  • Worldwide Sales and Service

28.6.2.4.1 Host Clock Generation

The SERCOM peripheral supports several I2C bidirectional modes:
  • Standard mode (Sm) up to 100 kHz
  • Fast mode (Fm) up to 400 kHz
  • Fast mode Plus (Fm+) up to 1 MHz
  • High-speed mode (Hs) up to 3.4 MHz
The Host clock configuration for Sm, Fm, and Fm+ are described in Clock Generation (Standard-Mode, Fast-Mode, and Fast-Mode Plus). For Hs, refer to Host Clock Generation (High-Speed Mode).

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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