21.8.10 Configuration n
Name: | CONFIGn |
Offset: | 0x18 + n*0x04 [n=0..1] |
Reset: | 0x00000000 |
Property: | Write-Protected |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
FILTEN7 | SENSE7[2:0] | FILTEN6 | SENSE6[2:0] | ||||||
Access | RW | RW | RW | RW | RW | RW | RW | RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
FILTEN5 | SENSE5[2:0] | FILTEN4 | SENSE4[2:0] | ||||||
Access | RW | RW | RW | RW | RW | RW | RW | RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
FILTEN3 | SENSE3[2:0] | FILTEN2 | SENSE2[2:0] | ||||||
Access | RW | RW | RW | RW | RW | RW | RW | RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
FILTEN1 | SENSE1[2:0] | FILTEN0 | SENSE0[2:0] | ||||||
Access | RW | RW | RW | RW | RW | RW | RW | RW | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 3, 7, 11, 15, 19, 23, 27, 31 – FILTENx Filter x Enable [x=7..0]
0: | Filter is disabled for EXTINT[n*8+x] input. |
1: | Filter is enabled for EXTINT[n*8+x] input. |
Bits 0:2, 4:6, 8:10, 12:14, 16:18, 20:22, 24:26, 28:30 – SENSEx Input Sense x Configuration [x=7..0]
SENSEx[2:0] | Name | Description |
---|---|---|
0x0 | NONE | No detection |
0x1 | RISE | Rising-edge detection |
0x2 | FALL | Falling-edge detection |
0x3 | BOTH | Both-edges detection |
0x4 | HIGH | High-level detection |
0x5 | LOW | Low-level detection |
0x6-0x7 | Reserved |
Note:
- FILTEN7-FILTEN0 bits and SENSE7[2:0]-SENSE0[2:0] bitfields in CONFIG0 register belong to External Interrupt 7 to 0.
- FILTEN7-FILTEN0 bits and SENSE7[2:0]-SENSE0[2:0] bitfields in CONFIG1 register belong to External Interrupt 15 to 8.