30.10.11 Status
| Name: | STATUS |
| Offset: | 0x0F |
| Reset: | 0x08 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYNCBUSY | STOP | ||||||||
| Access | R | R | |||||||
| Reset | 0 | 1 |
Bit 7 – SYNCBUSY Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bit 3 – STOP Stop Status Flag
This bit is set when the TC is disabled, on a Stop command, or on an overflow/underflow condition when the One-Shot bit in the Control B Set register (CTRLBSET.ONESHOT) is '1'.
| Value | Description |
|---|---|
| 0 | Counter is running. |
| 1 | Counter is stopped. |