14.3.1.8 Synchronization Delay

The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of:

Where $P_{\text{GCLK}}$ is the period of the generic clock and $P_{\text{APB}}$ is the period of the peripheral bus clock. A normal peripheral bus register access duration is $2\times P_{\text{APB}}$.