47.7.9 Debug control
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DBGCTRL |
| Offset: | 0x1E |
| Reset: | 0x00 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FDDBD | DBGRUN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 2 – FDDBD Fault Detection on Debug Break Detection
This bit is not affected by software Reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, and the on-chip debug (OCD) fault protection is disabled. When this bit is written to ‘1’, OCD break request from the OCD system will trigger non-recoverable fault.
| Value | Description |
|---|---|
| 0 | No faults are generated when TCC is halted in Debug mode. |
| 1 | A non recoverable fault is generated and INTFLAG.DFS (INTFLAG<11>) flag is set when TCC is halted in Debug mode. |
Bit 0 – DBGRUN Debug Running State
This bit is not affected by software Reset and should not be changed by software while the TCC is enabled.
| Value | Description |
|---|---|
| 0 | The TCC is halted when the device is halted in Debug mode. |
| 1 | The TCC continues normal operation when the device is halted in Debug mode. |