47.7.1 Control A
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Write-Synchronized (ENABLE, SWRST) |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CPTEN5 | CPTEN4 | CPTEN3 | CPTEN2 | CPTEN1 | CPTEN0 | ||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DMAOS | FCYCLE | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ALOCK | PRESCYNC[1:0] | RUNSTDBY | PRESCALER[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RESOLUTION[1:0] | ENABLE | SWRST | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 24, 25, 26, 27, 28, 29 – CPTENy Capture Channel y Enable
These bits are used to select the capture or compare operation on channel y (where y=0,1,2...5).
Writing a '1' to CPTENy enables capture on channel y.
Writing a '0' to CPTENy disables capture on channel y.
All these bits are enable-protected.
Bit 23 – DMAOS DMA One-Shot Trigger Mode
This bit enables the DMA One-shot Trigger Mode.
| Value | Description |
|---|---|
| 0 | Generate DMA triggers on each TCC cycle |
| 1 | Generate a DMA trigger on TCC cycle following a CTRLBSET.CMD(CTRLBSET<7:5>) = DMAOS command. |
Bit 16 – FCYCLE Full Cycle Enable
When this bit is set, TCC will wait for the end of the current cycle, to evaluate the stop condition.
This bit is enable-protected.
| Value | Description |
|---|---|
| 0 | The stop condition is evaluated immediately. |
| 1 | The stop condition is evaluated at the end of the cycle. |
Bit 14 – ALOCK Auto Lock
This bit is enable-protected.
| Value | Description |
|---|---|
| 0 | The Lock Update bit in the Control B register (CTRLBSET.LUPD (CTRLBSET<1>)) is not affected by overflow/underflow, and re-trigger events |
| 1 | CTRLBSET.LUPD (CTRLBSET<1>) is set to '1' on each overflow/underflow or re-trigger event. |
Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event.
These bits are enable-protected.
| Value | Name | Description | |
|---|---|---|---|
| Counter Reloaded | Prescaler | ||
| 0x0 | GCLK | Reload or reset Counter on next GCLK | - |
| 0x1 | PRESC | Reload or reset Counter on next prescaler clock | - |
| 0x2 | RESYNC | Reload or reset Counter on next GCLK | Reset prescaler counter |
| 0x3 | Reserved | ||
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TCC running in Standby mode.
These bits are enable-protected.
| Value | Description |
|---|---|
| 0 | The TCC is halted in standby mode. |
| 1 | The TCC continues to run in standby mode. |
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the Counter prescaler factor.
These bits are enable-protected.
| Value | Name | Description |
|---|---|---|
| 0x0 | DIV1 | Prescaler: GCLK_TCC |
| 0x1 | DIV2 | Prescaler: GCLK_TCC/2 |
| 0x2 | DIV4 | Prescaler: GCLK_TCC/4 |
| 0x3 | DIV8 | Prescaler: GCLK_TCC/8 |
| 0x4 | DIV16 | Prescaler: GCLK_TCC/16 |
| 0x5 | DIV64 | Prescaler: GCLK_TCC/64 |
| 0x6 | DIV256 | Prescaler: GCLK_TCC/256 |
| 0x7 | DIV1024 | Prescaler: GCLK_TCC/1024 |
Bits 6:5 – RESOLUTION[1:0] Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are enable-protected.
| Value | Name | Description |
|---|---|---|
| 0x0 | NONE | The dithering is disabled. |
| 0x1 | DITH4 | Dithering is based on overflow of a
4 bit-counter.
PER[3:0] and CCy[3:0] contain dithering pattern selection. |
| 0x2 | DITH5 | Dithering is based on overflow of a
5 bit-counter.
PER[4:0] and CCy[4:0] contain dithering pattern selection. |
| 0x3 | DITH6 | Dithering is based on overflow of a 6
bit-counter.
PER[5:0] and CCy[5:0] contain dithering pattern selection. |
Bit 1 – ENABLE Enable
Due to synchronization there is delay between when the CTRLA.ENABLE (CTRLA<1>) is written and the peripheral is enabled/disabled. The value written to CTRLA.ENABLE(CTRLA<1>) will be read back immediately and the ENABLE bit in the SYNCBUSY register (SYNCBUSY.ENABLE(SYNCBUSY<1>)) will be set. SYNCBUSY.ENABLE (SYNCBUSY<1>) will be cleared when the operation is complete.
| Value | Description |
|---|---|
| 0 | The peripheral is disabled. |
| 1 | The peripheral is enabled. |
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be disabled.
Writing a '1' to CTRLA.SWRST(CTRLA<0>) will always take precedence; all other writes in the same write-operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST(CTRLA<0>) until the reset is complete. CTRLA.SWRST(CTRLA<0>) and SYNCBUSY.SWRST(SYNCBUSY<0>) will both be cleared when the reset is complete.
- When the CTRLA.SWRST is written, the user should poll the SYNCB.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | There is no Reset operation ongoing. |
| 1 | The Reset operation is ongoing. |