48.6.1 Control A
- Only ENABLE and SWRST bits are Write Synchronized.
- Read/Write access to this register is limited to 32-bit width. Byte level access is not allowed.
- Reserved bits must always be written as ‘0’.
- TRAM module registers are not reset during a soft system reset.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLA |
| Offset: | 0x00 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SILACC | DRP | TAMPERS | ENABLE | SWRST | |||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SILACC Silent Access
Enables differential storage of data.
| Value | Description |
|---|---|
| 0 | Silent access is disabled. |
| 1 | Silent access is enabled. |
Bit 6 – DRP Data Remanence Prevention
Enables periodic Data remanence prevention (DRP) in the TRAM module.
| Value | Description |
|---|---|
| 0 | Data remanence prevention is disabled. |
| 1 | Data remanence prevention is enabled. |
Bit 4 – TAMPERS Tamper Erase
This bit enables auto-erase of the security RAM and DSCKEY bits (DSCC <29:0) on tamper event.
| Value | Description |
|---|---|
| 0 | Tamper erase is disabled. |
| 1 | Tamper erase is enabled. |
Bit 1 – ENABLE Enable
This bit is not Enable-Protected.
| Value | Description |
|---|---|
| 0 | The TRAM module is disabled. |
| 1 | The TRAM module is enabled. |
Bit 0 – SWRST Software Reset
Writing a ‘0’ to this bit has no effect.
Writing a ‘1’ to this bit resets all registers in the TRAM module to their initial state, and the TRAM module will be disabled. This bit can also be set via hardware when a tamper occurs while CTRLA.TAMPERS bit (CTRLA <4>) is set.
Writing a one to CTRLA.SWRST bit (CTRLA <0>) will always take precedence, meaning that all other writes in the same write operation will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST bit (CTRLA <0>) until the reset is complete. CTRLA.SWRST bit (CTRLA <0>) and SYNCBUSY.SWRST bit (SYNCBUSY <0>) will both be cleared when the reset is complete.
Reading this bit provides the following information.
- When the CTRLA.SWRST is written, the user should poll the SYNCB.SWRST bit to know when the reset operation is complete.
- During a SWRST, access to registers/bits without SWRST are disallowed until the SYNCBUSY.SWRST is cleared by hardware.
| Value | Description |
|---|---|
| 0 | The reset operation is not ongoing. |
| 1 | The reset operation is ongoing. |