48.6.7 Data Scramble Control

Note:

Access to this register is limited to 32-bit width. Byte level access is not allowed.
Reserved bits must always be written as '0'.

Table 48-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	DSCC
Offset:	0x18
Reset:	0x00000000
Property:	PAC Write-Protected, Enable-Protected


Bit	31	30	29	28	27	26	25	24
	DSCEN		DSCKEY[29:24]
Access	R/W		W	W	W	W	W	W
Reset	0		0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DSCKEY[23:16]
Access	W	W	W	W	W	W	W	W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DSCKEY[15:8]
Access	W	W	W	W	W	W	W	W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DSCKEY[7:0]
Access	W	W	W	W	W	W	W	W
Reset	0	0	0	0	0	0	0	0

Bit 31 – DSCEN Data Scramble Enable

Writing '1' to this bit enables the TRAM scrambling function. Reading this bit provides the following information:

Value	Description
0	TRAM scrambling function is disabled
1	TRAM scrambling function is enabled

Bits 29:0 – DSCKEY[29:0] Data Scramble Key

The key value used for address and data scrambling and descrambling. Any value written to this field is XOR’ed with the previous data. Writing ‘1’ to CTRLA.SWRST bit (CTRLA <0>) will reset this field to 0. These bits will always return ‘0’ when read.