18.6.2 External Multipurpose Crystal Oscillator (XOSC) Operation

The XOSC can operate in the following two modes:

• External clock with an external clock signal connected to the XIN pin.
• Crystal oscillator with an external 4-48 MHz crystal.

The XOSC can be used as a clock source for generic clock generators. This is configured by the Generic Clock Controller.

At reset, the XOSC is disabled, and the XIN/XOUT pins can be used as General Purpose I/O (GPIO) pins or by other peripherals in the system. When XOSC is enabled, the operating mode determines the GPIO usage. When in crystal oscillator mode, the XIN and XOUT pins are controlled by the OSCCTRL, and GPIO functions are overridden on both pins. When in external clock mode, only the XIN pins will be overridden and controlled by the OSCCTRL, while the XOUT pin can still be used as a GPIO pin.

The XOSC is enabled by writing a '1' to the Enable bit in the External Multipurpose Crystal Oscillator Control register (XOSCCTRLA.ENABLE). To enable XOSC as an external crystal oscillator, the XTAL Enable bit (XOSCCTRLA.XTALEN) must be written to '1'. If XOSCCTRLA.XTALEN is zero, the external clock input on XIN will be enabled.

If the External Multipurpose Crystal Oscillator AGC, Auto Gain Control, Loop (XOSCCTRLA.AGC) is '1', the oscillator gain will be automatically adjusted starting from lowest setting, and will increase the gain in sequential steps every XOSCCTRLB.GBW[1:0] delay for a maximum of 16 steps accordingly, until a valid stable oscillation is detected which will result in lowest power consumption for a stable crystal oscillation. In this mode, XOSCCTRLA.AGC =1, the manual XOSC crystal gain settings XOSCCTRLB.GMAN[1:0] are ignored.

The AGC Gain control loop update rate can be controlled by the XOSCCTRLB.GBW[1:0] user configuration bits. This controls the AGC delays between each gain step increase. Some unique crystals may have slow start-up times, so to insure the lowest power gain setting it may be necessary to increase the AGC gain step delay update rate to allow enough time for a slow crystal start-up to be realized and detected before increasing the XOSC gain step again. This is rare and 95% of all 4 MHz to 48 MHz crystals start-up with the default XOSCCTRLB.GBW[1:0] value.

Alternatively, if the External Multipurpose Crystal Oscillator Auto Gain Control Loop (XOSCCTRLA.AGC) is '0', the user can manually select the crystal oscillator operating condition by setting the manual gain value in the XOSCCTRLB.GMAN[1:0] register. In this mode, XOSCCTRLA.AGC = 0, XOSCCTRLB.GBW[1:0] AGC update rate is ignored.

Start-Up time, XOSCCTRLA.STARTUP, select the maximum start-up time for the oscillator XOSC before a clock fail is acknowledged. The OSCULP32K oscillator is used to clock the start-up counter for the XOSC. Start-Up Time.

The XOSC will behave differently in different sleep modes, based on the settings of XOSCCTRLA.ONDEMAND, and XOSCCTRLA.ENABLE. XOSCCTRLA.ONDEMAND must be written when XOSCCTRLA.ENABLE = 0. Otherwise, the write of this bit is ignored. If XOSCCTRLA.ENABLE = 0, the XOSC will be always stopped. For XOSCCTRLA.ENABLE = 1, this table is valid:

After a hard reset, or when waking up from a Sleep mode where the XOSC was disabled, the XOSC will need a certain amount of time to stabilize on the correct frequency. This start-up time can be configured by changing the Oscillator Start-Up Time bit group (XOSCCTRLA.STARTUP) in the External Multipurpose Crystal Oscillator Control register. During the start-up time, the oscillator output is masked to ensure that no unstable clock propagates to the digital logic. The External Multipurpose Crystal Oscillator Ready bit in the Status register (STATUS.XOSCRDY) is set when the external clock or crystal oscillator is stable and ready to be used as a clock source. The INTFLAG.XOSCRDY bit is set on a zero-to-one transition of STATUS.XOSCRDY and an interrupt is generated if the External Multipurpose Crystal Oscillator Ready bit in the Interrupt Enable Set register (INTENSET.XOSCRDY) is set. If the External Multipurpose Crystal Oscillator Auto Gain Control Loop (XOSCCTRLA.AGC) is set, and the XOSC fail to oscillate after attempting all gain settings, the External Multipurpose Crystal Oscillator Startup Fail bit in the Status register (STATUS.XOSCFAIL) is set. The INTFLAG.XOSCFAIL bit is set on a zero-to-one transition of STATUS.XOSCFAIL and an interrupt is generated if the XOSC Startup Failure bit in the Interrupt Enable Set register (INTENSET.XOSCFAIL) is set. After the the startup time has elapsed and the External Multipurpose Crystal Oscillator did not fail oscillating, the output clock can also be monitored for failure by using the Clock Fail Detector (CFD). Refer to next section for CFD operations.

USBHS Reference Clock Division

The XOSC oscillator is the source of the USBHS PLL's reference clocks. Each USBHS PLL can request the XOSC as a reference clock. Upon request by a USBHS, the XOSC clock is prescaled by a clock divider and issued to the USBHS PLL. The clock division ratio and enable is configured by the XOSCCTRLA.USBHSDIV bitfield.