18.6.5 Phase Locked Loop (PLL) Operation

The PLL provides a wide range of outputs from 12.7 MHz to 1600 MHz with support for input reference clock ranges from 4 MHz to 48 MHz. The PLL maintains a locked phase between the VCO input (reference) signal FPDF and the respective VCO output frequency FVCO through phase comparison and frequency multiplication.

The clocks from the PLL outputs (CLK_PLL) is a source for the Generic Clock module (GCLK).

Figure 18-2. PLL Block Diagram

Important: The frequency generated by the PLL oscillator can be up to 1600 MHz but is limited to 200 MHz (max.) for everything except inputs to FRACTIONAL DIVIDER. Depending on the operating conditions of the product using the PLL, the maximum allowed frequency can be as low as 12.7 MHz. Refer to the electrical characteristics of the product for a safe configuration of the PLL controller.