43.6.5.1 Dedicated Digital Filter
The Dedicated Digital Filter enables the ADC Module to feed a contiguous (i.e. back-to-back) set of input samples into a digital filter to produce a single finished output sample that either “averages” or “oversamples” the input samples. All the captured samples are equally weighted in the accumulation of the result before scaling of the final result.
The main difference between the “averaging” and “oversampling” modes relates to how the final filter output is scaled. Collecting 16 samples in “oversampling” mode generates two additional bits of output (14 bits total) while in “averaging” mode the output is always exactly 12 bits wide for all burst sizes.
The Digital Filter trades ADC throughput for increased data output resolution, in the sense that if random noise contaminates the least significant bits of a sample then “oversampling” can increase the resolution of the results. Oversampling by a factor of N increases the number of effective bits (ENOB) by square root(N). The scaling in “oversampling” mode for small N conserves all the data but for larger N some resolution is lost in order to fit the filters results into just 16 bits.
On the other hand, if the noise contamination of the samples is not random, but is harmonically related to another signal, this filtering will not improve ADC performance (ENOB does not change.).
Operation of the Digital Filter
The Digital Filter for ADCn must be enabled by setting FLTCTRLn.FLTEN. The input channel to be filtered, with index k, is set with FLTCTRLn.FLTCHNID = k . The choice between “averaging” or “oversampling” is implemented by FLTCTRLn.FMODE.
Once the Digital Filter is configured, the filter’s control logic waits for an external trigger of channel k to initiate the contiguous scan of samples defined by FLTCTRLn.OVRSAM. The trigger signal for the channel k to be filtered causes the accumulator to be cleared and initiates the first conversion.
On being enabled, the filter control logic has forced the trigger sensitivity into Level Mode (by logic appended to the internal registers associated with the CHNCFG1n.LVNk registers), which enables the selected ADCn to work in burst mode collecting back-to-back samples. The filter control logic will force internally the trigger to one as long as the filter needs more samples. In this way the ADCn itself will collect a burst of samples spaced apart according to CORCTRLn.SAMC.
When the required number of samples have been received and processed by the filter logic, the filter control logic releases the forcing of the channel trigger and starts waiting for a new initial sample (when the external trigger determines the sampling event according to the trigger waveform and the trigger setting to edge / level sensitivity).
At the completion of a burst collection the filter control logic will set the INTFLAGn.FLTRDY flag, which will trigger the ADCn interrupt if the corresponding bit in INTENSET has been set. Then the new output will be available using the CORCHDATAID and CHRDYDAT registers as described in ADC Result Registers.
Digital Filters Usage
To sustain the back-to-back collection of input samples the digital filter module will block any lower priority ADC conversion requests until the required input samples have been completed. However, any higher priority ADC requests will be processed un-impeded. Therefore, if higher priority requests occur during the filter sequence, the collected samples will no longer be contiguous, injecting unacceptable levels of aperture jitter over the burst and therefore contaminating the filter output. For this reason,the user should arrange the initiation trigger for the over burst collection to occur while there are no expected interruptions from higher priority ADC conversion requests.
The register field FLTCTRLn.FMODE determines the filtering mode. For “averaging” mode, FMODE=1. For “oversampling” mode, FMODE=0. When FMODE=1, the register field FLTCTRLn.DATA16EN controls the format of the filter’s output:
- FMODE=1 and DATA16EN=1, then the filter index output data is always left justified with all 16 bits significant.
- If FMODE=1 and DATA16EN=0, then the filter output data is always left justified but with only the first 12 bits significant and the last 4 bits always zero.
If FMODE=0 (i.e. when the Digital Filter works in accumulation mode), DATA16EN bit has no effect, but CHNCFG2n.FRACTk and CHNCFG3n.SIGNk determines the format of the filter output data as shown in Output Data Formats.
Digital Filters and the APB Bus FIFO
If PFFCTRL.PFFCRn is set for the ADCn using its Digital Filter the FIFO will capture all the back-to-back samples fed into the Digital Filter, save for the last scanned sample, which will be replaced by the filter’s output.
Finite Bursts
If the trigger of a burst collection is not repeated, then the ADC will collect just one burst. As long as the number of samples defined in OVRSAM is less than 16 then the samples collected will not overflow the FIFO. The first 15 will be directly available from the FIFO and, while the 16 sample is overwritten by the filter, the 16 sample can be recovered using the first 15 samples and the filter’s output.