34.8.7.2 Control B
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | CTRLB |
| Offset: | 0x04 |
| Reset: | 0x00000000 |
| Property: | PAC Write-Protection, Enable-Protected, Write-Synchronized |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FIFOCLR[1:0] | ACKACT | CMD[1:0] | |||||||
| Access | R/W | R/W | R/W | W | W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| QCEN | SMEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | |||||||||
| Reset |
Bits 23:22 – FIFOCLR[1:0] FIFO Clear
When these bits are set, the corresponding FIFO will be cleared. The bits will automatically clear when SYNCBUSY.SYSOP = 0.
These bits are not enable-protected.
| FIFOCLR[1:0] | Name | Description |
|---|---|---|
| 0x0 | NONE | No action |
| 0x1 | TXFIFO | Clear TX FIFO |
| 0x2 | RXFIFO | Clear RX FIFO |
| 0x3 | BOTH | Clear both TX/RX FIFO |
Bit 18 – ACKACT Acknowledge Action
This bit defines the I2C host's acknowledge behavior after a data byte is received from the I2C client. The acknowledge action is executed when a command is written to CTRLB.CMD, or if Smart mode is enabled (CTRLB.SMEN is written to one), when DATA.DATA is read.
This bit is not enable-protected.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Send ACK. |
| 1 | Send NACK. |
Bits 17:16 – CMD[1:0] Command
Writing these bits triggers a host operation as described below. The CMD bits are strobe bits, and always read as zero. The acknowledge action is only valid in Host Read mode. In Host Write mode, a command will only result in a repeated Start or Stop condition. The CTRLB.ACKACT bit and the CMD bits can be written at the same time, and then the acknowledge action will be updated before the command is triggered.
Commands can only be issued when either the Client on Bus Interrupt flag (INTFLAG.SB) or Host on Bus Interrupt flag (INTFLAG.MB) is '1'.
If CMD 0x1 is issued, a repeated start will be issued followed by the transmission of the current address in ADDR.ADDR. If another address is desired, ADDR.ADDR must be written instead of the CMD bits. This will trigger a repeated start followed by transmission of the new address.
Issuing a command will set the System Operation bit in the Synchronization Busy register (SYNCBUSY.SYSOP).
| CMD[1:0] | Direction | Action |
|---|---|---|
| 0x0 | X | (No action) |
| 0x1 | X | Execute acknowledge action succeeded by repeated Start |
| 0x2 | 0 (Write) | No operation |
| 1 (Read) | Execute acknowledge action succeeded by a byte read operation | |
| 0x3 | X | Execute acknowledge action succeeded by issuing a Stop condition |
These bits are not enable-protected.
Bit 9 – QCEN Quick Command Enable
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Quick Command is disabled. |
| 1 | Quick Command is enabled. |
Bit 8 – SMEN Smart Mode Enable
When Smart mode is enabled, acknowledge action is sent when DATA.DATA is read.
This bit is not write-synchronized.
| Value | Description |
|---|---|
| 0 | Smart mode is disabled. |
| 1 | Smart mode is enabled. |