27.5.4.3 Sleep Mode Controller

A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE[2:0]) select the level of the sleep mode.

Note: Due to clock domain synchronization a small latency occurs between the store instruction and actual writing of the SLEEPCFG.SLEEPMODE[2:0]. Software must ensure that the SLEEPCFG register reads the desired value of SLEEPMODE before issuing the WFI instruction.

Entry and exit from the various sleep modes is shown in the following table:

Table 27-2. Sleep Mode Entry and Exit
Mode	Mode Entry	Wake-Up Sources
IDLE	SLEEPCFG.SLEEPMODE = IDLE + WFI	Synchronous ⁽²⁾(APB, AHB), asynchronous ⁽¹⁾
STANDBY	SLEEPCFG.SLEEPMODE = STANDBY + WFI	Synchronous⁽³⁾, asynchronous ⁽¹⁾
HIBERNATE	SLEEPCFG.SLEEPMODE = HIBERNATE + WFI	Hibernate reset detected by the RSTC
BACKUP	SLEEPCFG.SLEEPMODE = BACKUP + WFI	Backup reset detected by the RSTC
OFF	SLEEPCFG.SLEEPMODE = OFF + WFI	External Reset

The sleep modes (Idle, Standby, Hibernate, Backup, and Off) and their effect on clock activity, regulators, and NVM state are described in the sections below. Refer to the Power Domain Controller section for the power domain gating effect.

Table 27-3. Modes of Operation
Mode	Main Clock	CPU	AHBx & APBx Clocks	GCLK Clocks	Oscillators ONDEMAND=		Regulators				NVM
Mode	Main Clock	CPU	AHBx & APBx Clocks	GCLK Clocks	0	1	VREGSW	VREGRAM	Addl. Regs	LPVREG	NVM
ACTIVE	Run	Run	Run	RiR⁽²⁾	Run	RiR⁽²⁾	On	On	On/Off⁽⁵⁾	Off	Active
IDLE	Run	Stop	Stop⁽¹⁾	RiR⁽²⁾	Run	RiR⁽²⁾	On	On	On/Off⁽⁵⁾	Off	Active
STANDBY	Stop	Stop	Stop⁽¹⁾	Stop⁽¹⁾	RiRR⁽³⁾	RiR⁽²⁾	On	LPM⁽⁴⁾	On/Off⁽⁶⁾	Off	LPM⁽⁴⁾
HIBERNATE	Stop	Stop	Stop	Stop	Stop	Stop	Off	LPM⁽⁴⁾	Off	Off	Off
BACKUP	Stop	Stop	Stop	Stop	Stop	Stop	Off	Off	Off	On	Off
OFF	Stop	Stop	Off	Off	Off	Off	Off	Off	Off	Off	Off

Note:

Stop except if running during Sleepwalking mode.
RiR = Run if Requested.
RiRR = Run if Requested or RUNSTDBY = 1.
LPM = Low-Power Mode.
On or Off, controlled by VREGCTRL.AVREGEN.
On or Off, controlled by (VREGCTRL.AVREGSTDBY = 1) && VREGCTRL.AVREGEN. If On then it will be in Low-Power mode.

Idle Mode

The IDLE mode allows power optimization with the fastest wake-up time.

The CPU is stopped, and peripherals are still working. As in Active mode, the AHBx and APBx clocks for peripheral are still provided if requested. As the main clock source is still running, wake-up time is very fast.

Entering Idle mode: The Idle mode is entered by executing the WFI instruction. Before entering the Idle mode, the user must select the Idle Sleep mode in the Sleep Configuration register (SLEEPCFG.SLEEPMODE = IDLE).

Additionally, if the SLEEPONEXIT bit in the Arm Cortex System Control register (SCR) is set, the Idle mode will be entered when the CPU exits the lowest priority ISR (Interrupt Service Routine. See Arm Cortex documentation for details). This mechanism can be useful for applications that only require the processor to run when an interrupt occurs.

Exiting Idle mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient priority to cause exception entry according to the PRIMASK register. The system goes back to the Active mode. The CPU and affected modules are restarted.

GCLK clocks, regulators, and RAM are not affected by the Idle Sleep mode and operate in normal mode.

Standby Mode

The Standby mode is the lowest power configuration while keeping the state of the logic and the content of the RAM.

In this mode, all clocks are stopped except those configured to be running Sleepwalking tasks. The clocks can also be active on request or at all times, depending on their on-demand and run-in-standby settings. Either synchronous (CLK_APBx or CLK_AHBx) or generic (GCLK_x) clocks or both can be involved in Sleepwalking tasks. This is the case when for example the SERCOM.CTRLA.RUNSTDBY bit is written to '1'.

Entering STANDBY mode: This mode is entered by executing the WFI instruction after writing the Sleep mode bit in the Sleep Configuration register (SLEEPCFG.SLEEPMODE = STANDBY).

Additionally, if the SLEEPONEXIT bit in the Arm Cortex System Control register (SCR) is set, the Standby mode will be entered when the CPU exits the lowest priority ISR (Interrupt Service Routine. This mechanism can be useful for applications that only require the processor to run when an interrupt occurs. Refer to the "Arm Cortex documentation" for details.

Exiting Standby mode: Any peripheral able to generate an asynchronous interrupt can wake up the system. For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous wake-up event occurs and the system is awakened, the device will either execute the interrupt service routine or continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the CPU. In Sleepwalking, a peripheral involved in the Sleepwalking task can wake up the system whatever the interrupt type (asynchronous or synchronous).

Hibernate and Backup Modes

Hibernate and Backup modes allow the lowest power consumption aside from off. The device is entirely powered off except for the VDDCORE_BU_PD domain. In Hibernate mode, the VDDCORE_RAM_PD power domain can be retained according to software configuration. All peripherals in backup domain are allowed to run, for example, the RTC can be clocked by a 32.768 kHz oscillator. All PM registers are reset except the CTRLA.IORET bit.

Entering Hibernate or Backup mode: This mode is entered by executing the WFI instruction after selecting the Hibernate or Backup mode by writing the Sleep Mode bits in the Sleep Configuration register (SLEEPMODE = HIBERNATE or = BACKUP).

Exiting Hibernate or Backup mode: This mode is triggered when a Hibernate or Backup Reset is detected by the Reset Controller (RSTC).

Note:

In Hibernate mode, the VREGRAM (in Low-Power mode) regulator is used to allow powering the VDDCORE_RAM_PD power domain which can be fully retained according to software configuration.
In Backup mode, the Backup Regulator (LPVREGC) is used.
Before entering Backup Sleep mode, it is recommended to poll the INTFLAG.SLEEPRDY bit to make sure that the backup regulator is ready. Let us say that the WFI instruction is executed whereas this flag is not set, then the system will go in a “pseudo backup mode where the VDDCORE_SW_PD power domain is turned off, but the VREGRAM is still used. Then the system will really go to Backup Sleep mode once the INTFLAG.SLEEPRDY field is set.
When WFI instruction is executed, before entering Hibernate or Backup, the PM waits until all the synchronous clocks have been properly turned off by MCLK and MCLK honors all clock requests from peripherals before turning off the synchronous clocks. Once there are no clock requests pending, the VDDCORE_SW_PD power domain can be turned off. Consequently, software is responsible to disable peripherals before executing the sleep instruction to avoid pending clock requests.
Let us say an interrupt occurs at the moment when the CPU is sleeping and MCLK is honoring a pending clock request then the device will wake up and the CPU can service the corresponding interrupt handler. The RCAUSE.BACKUP bit is zero as no backup reset has occurred.

Off Mode

In Off mode, the device is entirely powered off.

Entering Off mode: This mode is entered by selecting the Off mode in the Sleep Configuration register by writing the Sleep Mode bits (SLEEPCFG.SLEEPMODE = OFF), and subsequent execution of the WFI instruction after it is verified that the SLEEPMODE field has been set to Off mode.

Exiting Off mode: This mode is left by pulling the RESET pin low.