33.8.13 Event User m

Table 33-15. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: USERm
Offset: 0x0120 + m*0x01 [m=0..31]
Reset: 0x00000000
Property: PAC Write-Protection

Bit 76543210 
 CHANNEL[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:0 – CHANNEL[7:0] Channel Event Selection

These bits select channel n to connect to the event user m. The following table lists all of the Event Users and the associated 'm' value to determine which USERm register to define the desired Event Channel.

Note:
  1. A value x of this bit field selects channel n = x-1.
  2. By default, a channel is asynchronous. The Channel resynchronous path can be enabled if its index is < 12 and resynchronous selection is written to the CHANNEL.PATH bit field.
Table 33-16. Event User Mapping
User MacroUser MultiplexorUSER INDEXDescription Path Type (1)
FREQMSTART0Start MeasurementAR
RTCTAMPER1RTC TamperA
PORTEVx2-5PORT Event x=0..3AR
DMA0CHx-Start6-13Channel Start x=0..7AR
DMA0CHx-Aux14-21Channel Aux x=0..7AR
DMA1CHx-Start22-25Channel Start x=0..3AR
DMA1CHx-Aux26-29Channel Aux x=0..3AR
TCC0EVx30,31EV x=0..1AR
MCx32-37MC x=0..5AR
TCC1EVx38,39EV x=0..1AR
MCx40-45MC x=0..5AR
TCC2EVx46,47EV x=0..1AR
MCx48-53MC x=0..5AR
TCC3EVx54,55EV x=0..1AR
MCx56-61MC x=0..5AR
TCC4EVx62,63EV x=0..1AR
MCx64,65MC x=0..1AR
TCC5EVx66,67EV x=0..1AR
MCx68,69MC x=0..1AR
TCC6EVx70,71EV x=0..1AR
MCx72,73MC x=0..1AR
TCC7EVx74,75EV x=0..1AR
MCx76,77MC x=0..1AR
ADCTRIGx78-88ADC TRIG x=0..10A
ACSOCx89,90AC SOC x=0..1AR
PTCDSEQR91-A
STCONV92-A
CCLLUTIN_x93-96LUTx Input, x=0…3AR
PDECEVU_x97-99EVUx , x=0…2AR
HSMTAMPERx100-103TAMPER x =0...3 A
Note:
  1. A = Asynchronous path, R = Resynchronized path