58 Revision History

Revision H - March 2026


Section	Description
General	Updated all references of AXI to AHB throughout the document
Up to 2 MB Live-Update Flash and 512 KB SRAM with Hardware Security Module (HSM) for Secure Connectivity Applications	Updated Temperature in Operating Conditions
Package and Pinout	Updated the 48-pin Table
Signal Description	Updated all tables in this section to include new specs for the 48-pin VQFN
Power Supplies and Startup Considerations	Updated VDDUSB to VUSB3V3 in the following sections: Power Domain Overview Power Supplies Power-on Reset (POR) and Brown-out Reset (BOR)
Memories	Added a note to FUCFG9 and redefined it
Hardware Security Module (HSM)	Updated the RAM specifications in Features.
Device Service Unit (DSU)	Updated the CPUx bitfield description in the DAL Register
Main Clock (MCLK)	Removed erroneous text from Main Clock Removed the Clock Domains section Removed erroneous information from Principle of Operation Removed the Selection the Synchronous Clock Division Ratio section Clarified verbiage in Clock Ready Flag Clarified verbiage in Interrupts Removed an erroneous Register, Clock Divide n Register Redefined bitfields in the following registers: CLKMSK0 CLKMSK1 CLKMSK2 CLKMSK3
Direct Memory access Controller (DMAC)	Added a note to Arbitration for PORT Resources Removed the Event System Priority Increase section Updated the CTRLB Register with new bitfield numbering and notes Updated the CHCTRLBk Register with a new note on the BYTORD bitfield and redid the table for the PR bitfield Updated the CHEVCTRLk register with table updates to the EVAUXACT bitfield Updated the CHCTRLCRCk with new verbiage for the CRCROUT and CRCXOR bitfields
Power Manager (PM)	Added a new note to the RAMCFG bitfield in the STDBYCFG and HIBCFG Registers
External Interrupt Controller (EIC)	Added a note to External Pin Processing
Ethernet Media Access Controller (ETH)	Added a note to Partial Store and Forward Using Packet Buffer DMA
Event System (EVSYS)	Added a note to Sleep Mode Operation Updated the USERm Register to display eight bits, and revised part of the Event User Mapping table
I/O Pin Controller (PORT)	Added a note to Events
Universal Serial Bus Hi-Speed (USBHS)	The following registers were restructured with renumbered bitfields: INTRTX INTRRX INTRTXE INTRRXE CSR0L
SD/MMC Host Controller (SDHC)	Updated the following registers, removed erroneous bits or added new verbiage: HC1R NISTR EISTR EISTER EISIER CA0R CA1R ACR
Configurable Custom Logic (CCL)	Updated the INSELy bitfield in the LUTCTRLn Register with new data in the bitfield table
Analog-to-Digital Converter (ADC)	Updated the ADCHSEL bitfield table in the CTRLB Register to reflect new values for the ADC module
Timer/Counter for Control Applications (TCC)	Updated the following registers with new bitfield definitions: EVCTRL INTENCLR INTENSET INTFLAG WAVE
Electrical Characteristics 85°C	Updated Min, Typ, and Max specifications in the tables for the following sections: Power Supply MCU Active Power MCU Idle Power MCU Standby Power
Electrical Characteristics 125°C	Added the following new sections: MCU Active Power MCU Idle Power MCU Standby Power

Revision G - June 2025


Section	Description
Up to 2 MB Live-Update Flash and 512 KB SRAM with Hardware Security Module (HSM) for Secure Connectivity Applications	Added in new temperature range for Operating Conditions
Package and Pinout	Updates to Signal Names for the EIC, PTC, and CAN were implemented for the following tables: 48-Pin VQFN Packages 64-Pin TQFP/VQFN Packages 100-Pin TQFP Package 144-Pin TQFP Package 144-Pin TFBGA Package
Signal Description	Replaced the Serial Communication Interface (SERCOM) Signals table with a new table
Multi-Channel RAM Controller (MCRAMC)	All new updated chapter
Clock Distribution System	Added a new note to Overview for asynchronicity
PORT	Added the following Registers: INTENCLR INTENSET INTFLAG NONSEC NSCHK
WDT	Updated the EWOFFSET bitfield of the EWCTRL Register with a new signal name, replacing GCLK_WDT with CLK_WDT_OSC
DMAC	Updated the Register output for all Channel k Registers to properly display in the Register Summary
ETH	Updated the table in Signal Interface, replacing ETH_TXCK1 with ETH_TX_CLK
SERCOM USART	Updated the bit value from 8 to 16 in the Clock Generation Diagram in Clock Generation and Selection Updated Parity to include 0x5 for error checking Updated the PMODE bit in the CTRLB Register
SERCOM I²C	Added a Table to the Block Diagram for I²C Pad Descriptions.
TCC	Updated the Diagram for the Circular Buffer
Electrical Characteristics 85°C	Added note 4 to the following sections: Non-Volatile Memory Controller (NVM) Electrical Specifications Universal Serial Bus (USB) Electrical Specifications Added in new diagrams to the following sections: MCU Active Power MCU Idle Power MCU Standby Power
Electrical Characteristics 125°C	All new Electrical Specifications chapter

Revision F - December 2024


Section	Description
Up to 2 MB Live-Update Flash and 512 KB SRAM with Hardware Security Module (HSM) for Secure Connectivity Applications	Removed erroneous 512K references
Pinout	Updated the table titles in 64-Pin TQFP Packages to correct the family name Updated the table titles in 100-Pin TQFP Packages to correct the family name and updated erroneous VSS references to new Pad names
Product Mapping	Removed erroneous 512K content from the following sections: Code Address Space SRAM Address Space Peripheral Address Space External RAM Address Space
Memories	Updated the Physical Memory Map with a new table

Revision E - October 2024


Section	Description
Configuration Summary	Added new tables to reflect new package offerings
Package and Pinout	Added a new pinout for the 144-pin TFBGA and 48-pin VQFN
Signal Descriptions	Updated all tables to display new pin counts for the 48-pin TQFP and 144-pin TFBGA
Power Supplies and Startup Considerations	Updated Table 7-1 with new signal names Updated the Power Domain Block Diagram with new signal names Updated Power Domain Constraints with new signal names Updated Signal names for figure 7-2 in Typical Powering Schematic Updated signal names in Supply Order
Memories	Added a note to FUCFG3
SUPC	Added a note to Overview Updated the Block Diagram with new signal names
RSTC	Updated the BORVDDA bitfield of the RCAUSE Register with a new note
PORT	Added a new table to the PMUXm Register
TCC	Added timers descriptions to the Overview Added a new column for Counter Size to the Feature Summary Updated the number of comparators in the Block Diagram Added notes to the following Registers: PER CCy PERBUF CCBUFy
CCL	Added a note to the INSELy bitfield of the LUTCTRLn Register
ADC	Updated the input Signal names from AIN to VINP throughout the chapter
Electrical Characteristics (85°C)	Added in the 144-pin TFBGA package for the Thermal Packaging Characteristics table Updated signal names in Analog-to-Digital Converter (ADC) Electrical Specifications
Packaging	Added a new 48-pin VQFN Added a new 144-pin TFBGA Package

Revision D - July 2024


Section	Description
Package and Pinout	Updated the following Pinouts updating VCCAPP3 to VUSB3V3: 100-pin TQFP 144-pin TQFP
Signal Description	Updated Table 6-13 PORTA through PORTD Signals with a new pin number for PB00
Clock Distribution System	Updated the Clock Distribution Block Diagram converting MCLK to GCLK
TrustRAM (TRAM)	Updated the Overview with a new value for the security RAM Updated the Address Count in the diagram for Data Remanence Prevention Updated the RAM register with a new offset equation
Electrical Characteristics (85°C)	Added eight new graphs for IOH, VOL, VOH, and IOL to the I/O Pin Electrical Specifications

Revision C - April 2024


Section	Description
General	Minor changes of format. VREFP0 changed by VREFH SPIxC- TRL changed by SPIxCTRL VDDF changed by VDDFLASH ADC0 changed by ADC ADCn changed by ADC INSELx changed by INSELy Remove VBAT references
Features	Updated info of USB2.0 and Advanced Analog Features and Touch. Removed NIST compliant information.
Configuration Summary	Updated Brown-out Detection info in: Table 1-1 and Table 1-2
Guidelines for Getting Started	Replaced Pie-Filters by Pi-Filters in the EMI/EMC/EFT (IEC61000-4-4 and IEC 61000-4-2) Suppression Considerations section
Package and Pinout	Updated MISC column in: Table 5-6 Table 5-8 Table 5-9
Signal Description	Added info of 64-Pin and 100-Pin in all the tables
Power Supplies and Startup Considerations	Removed VBAT in Figure 7-1
Product Mapping	Removed Base Address in: Table 8-5 Table 8-6 Table 8-7 Table 8-8
Peripherals	Updated Figure 9-1
Processor and Architecture	Modified format of Table 10-2 and added note
Memories	0x0054 is Reserved in User Configuration Map Updated FUCFG5 - User Configuration Register 5 – Reserved
Cortex-M Cache Controller (CMCC)	Updated table in Peripheral Dependencies section Updated reference section in Tightly Coupled Memory section Minor changes in Cache Invalidate by Line Operation section Minor changes in Cache Performance Monitoring section
Peripheral Access Controller (PAC)	Updated table in Peripheral Dependencies section Removed bullet in the Register Access Protection section
Device Service Unit (DSU)	Updated Features section Added notes in Signal Description section Updated table in Peripheral Dependencies section Updated first paragraph in Cold Plugging Removed reference in Boot Communication Channels section
Clock Distribution System	Updated Figure 18-1 Minor changes in Overview section
Oscillator Controller (OSCCTRL)	Updated table in Peripheral Dependencies section Replaced XOSCCTRLB[3] by XOSCCTRLB.GBW[1:0] and XOSCCTRLB[1:0] by XOSCCTRLB.GMAN[1:0] in External Multipurpose Crystal Oscillator (XOSC) Operation section Replaced DFLL48M Loose Lock by DFLL48M Lose Lock After Wake and added note in Additional DFLL48M Features section Added note in XOSCFAIL bitfield in the STATUS Register Added note in BWSEL bitfield in the PLL0CTRL Register Added note in POSTDIVn bitfield in the PLL0POSTDIVA Register
Generic Clock Controller (GCLK)	Updated Generic Clock Generators to 12 and updated Peripheral Channels to 48 Updated the Peripheral Clock Added Enabling a Peripheral Clock Added note 5 in the Selecting the Clock Source for a Peripheral section Updated the GENCTRLn Register Updated PCHCTRLm Register
Main Clock (MCLK)	Updated Synchronous Clock Selection
32 KHz Oscillators Controller (OSC32KCTRL)	Updated bits of XOSC32K.STARTUP in 32 kHz External Crystal Oscillator (XOSC32K) Operation section
Frequency Meter (FREQM)	Minor changes of format in Overview and Measurement sections Added notes in SWRST bitfield in the CTRLA Register Added note in REFNUM bitfield in the CFGA Register
Real-Time Counter (RTC)	Updated Figure 25-3 Minor changes in Active Layer Protection section Added Important note in CTRLA Register
Direct Memory Access Controller (DMAC)	Updated channels of DMA Controller modules 0 and 1 Updated DMA Event/Trigger Mapping
Supply Controller (SUPC)	Updated Features section Minor changes in Block Diagram section and removed VBAT in Figure 27-1 Updated table in Peripheral Dependencies section Removed Battery Backup Power Switch section Added note in LVHIB bitfield in the VREGCTRL Register Added note in LPHIB and LPSTDBY bitfields in the VREFCTRL Register
Power Manager (PM)	Updated VREGSW in Table 28-3 Updated the Standby Mode section Updated the Hibernate and Backup Modes section Removed a sentence in I/O Line State Retention in Hibernate and Backup Modes section
Reset Controller (RSTC)	Removed VBAT reference in Features and the Reset Causes and Effects sections
External Interrupt Controller (EIC)	Replaced EXTINTx by EIC_EXTINTx in Figure 30-1 Minor changes in Initialization section Added note in NMIFLAG Register
Event System (EVSYS)	Minor changes in Edge Detection section Added Important note in PATH bitfield in CHANNELn Register
Serial Communication Interface (SERCOM)	Minor changes of format in Clock Generation – Baud-Rate Generator section Updated FIFO Operation section
Serial Quad Interface (SQI)	Updated Chip Selects to 4 Updated Figure 36-1 Updated CSEN bitfield in CFG Register
Universal Serial Bus Hi-Speed (USBHS)	Minor changes of format in Overview section Replaced UPLLFSEL by CTRLA.REFCLKSEL in Block Diagram section Removed OTG in Signal Description section
Controller Area Network (CAN)	Updated number of CAN in Features section Updated note in Block Diagram section Updated Table 39-1 Minor changes in the Clocks section
True Random Number Generator (TRNG)	Updated second paragraph in Overview section Removed one bullet in Features section
Configurable Custom Logic (CCL)	Removed Timer/Counter Inputs (TC) section Removed note in Timer/Counter for Control Application Inputs (TCC) section Updated INSELy bitfield in LUTCTRLn Register
Analog-to-Digital Converter (ADC)	Updated Overview section Updated Features section Removed note in Block Diagram section Removed note 3 in Singnal Description section Added Important note in Conversion Timing and Sampling Rate section Updated Initialization section Updated Interrupts section Updated Events section Updated SWCNVEN, SAMP and RQCNVRT bitfields in CTRLB Register Removed VBAT reference in ADCHSEL bitfield in CTRLB Register Bits 14 and 30 as reserved in CONFIG[0].CHNCFG1 Register Updated LVLk and CHNCMPEk bitfields in CONFIG[0].CHNCFG1 Register Updated FRACk and CSSk bitfields in CONFIG[0].CHNCFG2 Register Updated note 5 of TRGSRCk bitfield in CONFIG[0].CHNCFG4 and CONFIG[0].CHNCFG5 Registers
Analog Comparators (AC)	Updated MUXPOS bitfield in COMPCTRL0 Register
Position Decoder (PDEC)	Minor changes in Secure Decoder Detection section Updated Re-trigger Software Command or Event Action section Updated EVACT bitfield in EVCTRL Register
Timer/Counter for Control Applications (TCC)	Updated number of TCC in Overview section Updated number of Compare/Capture Channels in Features Updated values of table in the Feature Summary section Updated table in Signal Description section Updated value of TCC bus clocks in the Clocks section Updated Principle of Operation section Minor changes in Initialization, Enabling, Disabling, and Resetting, Prescaler Selection, Counter Operation and Circular Buffer sections Removed last paragraph of Stop Command in Counter Operation section Added note in Alternate RAMP2 (RAMP2A) Operation section Updated Table 48-4 Added Important note in DMA Operation section Updated CPTEN bitfield in CTRLA Register Added note in DIR bitfield in CTRLBSET Updated CC bitfield in SYNCBUSY Register Updated CCBUFV and CMP bitfields in STATUS Register Updated CCy Register Updated CCBUFy Register
TrustRAM (TRAM)	Added note 4 in CTRLA Register Added note 2 in CTRLA Register
Peripheral Touch Controller (PTC)	Minor changes in Clocks section
Electrical Characteristics (85°C)	Updated Note 4

Revision B - May 2023


Section	Description
General	Updated DPLL to read PLL throughout the document
Features	Updated Advanced Analog Features and Touch instances with new data for channel numbers Reformatted the Communication Interfaces/Digital Peripherals section Updated the DMA instances
Configuration Summary	Replaced the existing tables with all new content
Signal Description	Replaced the existing tables with all new content
Block Diagram	Updated the Diagram with a new image
Pinout	Updated the following Pinout tables with all new content: 144-pin TQFP 100-pin TQFP 64-pin QFN and TQFP
Power Supplies and Startup Considerations	Updated the table in Power Supplies and Startup Considerations with new valued for the VDDREG Updated the bulleted items in Power Domain Constraints removing references to VDDCORE_USB1 and VDDUSB1 Updated the bulleted items in Power Supplies removing references to VDDUSB3V1 Renamed Boot ROM to Boot Flash (BFM) in Initial Instructions Fetching Updated VDDREG verbiage in Supply Order Updated I/O Pins with all new verbiage
Processor and Architecture	Removed the erroneous Overview section Updated NVIC Interrupt Line Mapping to remove ULDOOVHEAT and ULDORDY
Memories	Updated the Physical Memory Map Added s new section, PFM Error Correction Removed erroneous references to DAL and DAL-CFG in Configuration Flash Memory Removed an erroneous section pertaining to DAL Configuration Removed an erroneous section pertaining to CAL-OTP Configuration
CMCC	Updated the WAYNUM bitfield in the TYPE Register with a new table
IDAU	This chapter was completely rewritten in this revision
DSU	Corrected erroneous bitfield output for the CPUx bitfield in the DAL Register Removed an obsolete DATA Register Summary and associated Register
Clock Distribution System	Updated the Block Diagram with an all new image Updated the Diagram Example of a SERCOM_0 Clock to remove erroneous DPLL references
OSCCTRL	Removed erroneous clock references from the Block Diagram Updated Phase Locked Loop (PLL) Operation to remove erroneous Digital references Removed the following erroneous registers: DPLL1CTRL DPLL1FBDIV DPLL1REFDIV DPLL1POSTDIVA FRACDIV1 Added a new register, PLL0POSTDIVB
GCLK	Updated Figure 19-3 in Generic Clock Generator, changed DPLL to PLL and removed erroneous clock signals Corrected erroneous bitfield output in the following registers, and/or updated bitfield descriptions: SYNCBUSY GENCTRLn PCHCTRLm
MCLK	Added a new register, CLKDIV
OSC32KCTRL	Updated the CGM and STARTUP bitfields to properly display content in the XOSC32K Register
WDT	Updated the following registers to properly display bitfield information: EWCTRL
RTC	Updated the TAMPCTRL Register to properly display the INnACT bitfield output
SUPC	Removed erroneous LDO information from the Block Diagram Removed erroneous bitfields for ULDOOVHEAT, and ULDORDY from the following registers: INTENCLR INTENSET INTFLAG STATUS Removed erroneous bitfields for BKUP_VLD, SRAM_VLD, ULDOLEVEL, ULDSTDBY, ULDOEN, and OFFSTDBY from the VREGCTRL Register Added new information for the LVSTDBY and VREGOUT bitfields in the VREGCTRL Register
RSTC	Updated Reset Causes and Effects to remove an erroneous reference to BOD33
NVMCTRL	Replaced the image for the Block Diagram Updated Configuration Flash Memory to remove erroneous DALCFG, CAL, and SDAL references
ADC	Updated throughput rates for the ADC in Features Removed erroneous cores from the ADC block diagram, removed references to other modules from the ADC Trigger Block Diagram Updated the verbiage in the Signal Description to remove erroneous mentions to modules Updated the following registers with new naming conventions and/or verbiage updates to bitfields, including new notes and tables: CONFIG[0].CORCTRL CONFIG[0].CHNCFG1 CONFIG[0].CHNCFG2 CONFIG[0].CHNCFG3 CONFIG[0].CHNCFG5 CONFIG[0].CALCTRL EVCTRL0 FLTCTRL0 CORCHDATAID PFFDATA SYNCBUSY INTENCLR INTFLAG Added a new note to the CTRLC Register for the CNT bitfield
Electrical Specifications 85°C	Updated the typ specifications for Wake-Up Timing Updated FCLK_31 in Maximum Clock Frequencies Updated Xosc_3 and XOSC_5, and added XOSC_39 to External Oscillator (XOSC) Electrical Specifications Updated DFLL/PLL Electrical Specifications with new min, typ, and max specifications Updated the tables in Analog-to-Digital Converter (ADC) Electrical Specifications with new min, typ, and max specifications Replaced the tables in Comparator Electrical Specifications Updated Peripheral Touch Controller (PTC) Electrical Specifications with new max specifications Updated I²S Host Mode AC Electrical Specifications with a new max specification for I2S_33 Updated Timer Counter for Control Application (TCC) Electrical Specifications with a new max specification for TCC_15 Updated Non-Volatile Memory Controller (NVM) Electrical Specifications with a new min specification for NVM_3 Updated max specifications for SD_5 and SD_25 in SD/MMC Host Controller (SDHC) Electrical Specifications Updated min and max specifications in JTAG Electrical Specifications Updated SWD_1 max specifications in SWD 2-Wire Electrical Specifications
Extended Temperature Electrical Characterstics (125°C)	All new section
Schematic Checklist	Updated the voltage specifications in the Diagram in Introduction
Packaging	Updated the following packages with new images and/or new information: 64-pin TQFP 64 Lead VQFN 100 Lead TQFP 144 Lead TQFP

Revision A - November 2022

Terminology used in this document may not match with the contents of other Microchip documentation and collateral. For any questions or concerns regarding terminology, contact a Microchip support or sales representative.

This is the initial released version of this document.