11.7 CAL OTP Configuration
The following values are programmed at the Factory and cannot be changed.
| Address | Register | Module | Bitfield |
|---|---|---|---|
| Base + 0x080 | FCCFG0 | SUPC | CFG_SMOR0[31:0] |
| Base + 0x080 | FCCFG1 | SUPC | CFG_SMOR0[31:0] |
| Base + 0x0A0 | FCCFG8 | SUPC/OSC32KCTRL |
[15:0] - CFG_DSSMOR_REF[15:0] [31:16] - CFG_DSSMOR_CLK[15:0] |
| Base + 0x0C0 | FCCFG16 | OSCCTRL | CFG_DFLL48M[31:0] |
| Base + 0x0C4 | FCCFG17 | OSCCTRL |
[15:0] - CFG_XTAL[15:0] [31:16] - RSVD |
| Base + 0x0E0 | FCCFG24 | SUPC |
[15:0] – CFG CALVREGSW0[15:0] (99ma) [31:16] – CFG CALVREGSW1[15:0] (99ma) |
| Base + 0x0E8 | FCCFG26 | SUPC |
[15:0] – CFG CALADDVREG0[15:0] ( 50 ma) [31:16] – RSVD |
| Base + 0x0EC | FCCFG27 | SUPC |
[15:0] – RSVD [31:16] - CFG_CALVREGRAM[15:0] ( 50 ma) |
| Base + 0x0F0 | FCCFG28 | SUPC |
[3:0] - CALCP[3:0] [7:4] - RSVD [15:8] - CALSUPC[7:0] [31:16] - RSVD |
| Base + 0x0F4 | FCCFG29 | SUPC |
[7:0] - CALUSERLDO[7:0] [31:8] - RSVD |
| Base + 0x100 | FCCFG32 |
DSU[DID] DSU[DCFG0] |
[7:0] - RSVD [3:0] , PFM_SZ[3:0] , [15:8] - DRM_SZ [7:0] [23:16] - RSVD[3:0] ,FPACKAGE[3:0] [31:24] - DID_DEVSEL[7:0] |
| Base + 0x104 | FCCFG33 | DSU[DCFG1] |
[7:0] – ME_HSM, DPA, RSVD, ME_SPI_IXS, RSVD, ME_SQI, ME_SDMMC1, SDMMC0 [15:8] – ME_TCC7, ME_TCC6, ME_TCC5, ME_TCC4, ME_TCC3, ME_TCC2, ME_TCC1, ME_TCC0 [23:16] – ME_SERCOM5, ME_SERCOM4, ME_SER-COM3, ME_SERCOM2, ME_SERCOM1, ME_SER-COM0, RSVD[1:0] [31 :24] – ME_EBI, ME_PCC, ME_ETH, ME_PTC, RSVD[1:0], ME_SERCOM7, ME_SERCOM6 |
| Base + 0x108 | FCCFG34 | DSU[DCFG2] |
[7:0] – RSVD[5:0], ME_CAN1, ME_CAN0 [15:8] - ME_DMA0CH[5:0], ME_USBFS, ME_USBHS0 [23:16] - ME_DMA1CH[5:0], RSVD, ME_PDEC [31:24] – RSVD (for ME_ACPAIR_SEL[7:0]) |
| Base + 0x144 | FCCFG49 | MBISTINTF | MEM_MARGIN0[31:0] |
| Base + 0x148 | FCCFG50 | MBISTINTF | MEM_MARGIN1[31:0] |
| Base + 0x14C | FCCFG51 | MBISTINTF | MEM_MARGIN2[31:0] |
| Base + 0x160 | FCCFG56 |
BOOTROM -> RPMU [BRRPMU_CAL] | BRRPMU_CAL[31:0] |
| Base + 0x164 | FCCFG57 |
BOOTROM -> RPMU [BRCFGPWSAKDLY] | BRCFGPWSAKDLY [31:0] |
| Base + 0x168 | FCCFG58 |
BOOTROM -> RPMU [BRCFGRINGOSC] | BRCFGRINGOSC [31:0] |
| Base + 0x16C | FCCFG59 | BOOTROM | RESERVED |
| Base + 0x180 | FCCFG64 | User SW => PTC |
[2:0] PTC_CALIB_PTC_IBIAS_TRIM [3] PTC_CALIB_PTAT_EN [4] PTC_CALIB_EXT_IBIAS_EN [13:5] SPARE [15:14] PTC_CALIB_ADC_T1_DLY [31:16] RESERVED |
| Base + 0x184 | FCCFG65 | User SW => ADC |
[0] ADC_CALCTRL_EN_CMBF [1] RESERVED [2] ADC_CALCTRL_EN_DITHER [3] ADC_CALCTRL_DIS_FAZ [4] ADC_CALCTRL_DIS_SAZ [5] ADC_CALCTRL_DIS_LAZ [6] ADC_CALCTRL_EN_RDAC [7] ADC_CALCTRL_DBG_SEL [8] ADC_CALCTRL_SEL_DEL [10:9] ADC_CALCTRL_T1_DLY [15:11] ADC_CALCTRL_TCLK_DIV [19:16] RESERVED [21:20] ADC_CALCTRL_IADC1 [23:22] ADC_CALCTRL_IADC2 [25:24] ADC_CALCTRL_ICMP1 [27:26] ADC_CALCTRL_ICMP_2 [29:28] ADC_CALCTRL_ICMBF [30] RESERVED [31] ADCFG0 |
| Base + 0x188 | FCCFG66 |
User SW => AC (CTRLC) |
[7:0] – RSVD [7:4], CONFIG[3:0] [31:8] - RSVD |
| Base + 0x18C | FCCFG67 | User SW => USBHS Squelch |
[3:0] CFG_USB_PHY_SQUELCH [11:4] CFG_USB_PHY_TUNE [14:12] CFG_USB_PHY_ODT [17:15] CFG_USB_PHY_HSSLEW [21:18] CFG_USB_PHY_DISCONDET [24:22] CFG_USB_PHY_HSDRVCOMP [31:25] RESERVED |
| Base + 0x190 | FCCFG68 | User SW => USBFS.PAD-CAL |
[4:0]: TRANSP[4:0] [5]: RSVD [10:6]: TRANSN[4:0] [11]: RSVD [14:12] TRIM[2:0] [31:15]: RSVD |
| Base + 0x1A0 | FCCFG72 | User SW => ETH | FMAC[31:0] |
| Base + 0x1A4 | FCCFG73 | User SW => ETH |
[15:0] - FMAC[47:32] [31:16] - RSVD[15:0] |