Updated IP core top-level
DQ_ECC port bit mapping to device package pin FDDR_DQ_ECC[#] for proper ECC
functionality.
RTG4 DDR DQ works as expected
when SECDED is enabled.
When opening a pre-2025.1 RTG4
design that uses the RTG4 FDDR in x16 or x8 modes, the design is invalidated
to a pre-synthesis state.
Applicable for designs that
contain instances of the RTG4FDDRC or RT4FDDRC_INIT core configured for
16-bit or 8-bit DQ width with ECC enabled.
The core component must be
updated to an RTG4 version 2.0.200 or later and regenerated to continue with
the design flow.
Review the latest RTG4 Package
Pin Assignment Table (PPAT) available on the Microchip website to ensure the
board layout has connected the correct FDDR_<E|W>_DQ_ECC<#>
package pin to the DDR memory device holding ECC data, depending on the DQ
bit-width in use.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
