Updated the rules for selecting the
high-VCO frequency used to implement the enhanced PLL calibration introduced along
with CN19009 and its addendums.
Prior to v2.2.100, the
allowed ratio of high-VCO frequency to actual-VCO frequency used during PLL
calibration was between 1.5x to 1.9x of the user configured actual-VCO
frequency.
Starting with v2.2.100, the
allowed High-VCO frequency selected by the RTG4FCCCECALIB core is limited to
the reduced range of 1.25x to 1.5x of the actual-VCO frequency. The change
was applied to mitigate a rarely encountered loss of lock at cold operating
temperatures for specific core configurations using VCO speed-up ratios on
the higher side of the previously allowed range.
Reduced the enhanced PLL calibration
high-VCO dwell time from 150 us to 100 us in the RTG4 SerDes PCIe/XAUI SPLL
calibration sequence used with a CoreABC initialization subsystem, to ensure
continued successful PCIe endpoint enumeration on newer generation host CPUs. The
same update was applied to the RTG4FCCCECLAIB and FDDR cores to ensure consistency
for all cores using PLL calibration.
Recommended actions related to the
PLL Calibration updates:
No action is required for:
Designs that have
successfully completed full functional and system testing on each
production unit over the full operating conditions.
Designs not using the
PLL in RTG4FCCECALIB, the FDDR FPLL, or the SerDes SPLL
(PCIe/XAUI).
For ongoing designs using
fabric PLLs in systems where the operating temperature can fall below 0°C,
perform the following steps and re-run the design flow:
Upgrade the design to
Libero SoC v2025.1, and observe a warning message in the log
window.
Update instances of
RTG4FCCCECALIB to v2.2.100 and regenerate the core.
Update instances of
RTG4FDDRC or RTG4FDDRC_INIT to v2.0.200 and regenerate the core.
For
RTG4FDDRC, manually copy the updated FDDR_init.txt
initialization program into the user CoreABC initialization
subsystem.
Update instances of
RTG4 SerDes cores using the SPLL (for PCIe or XAUI interfaces) to
v2.0.200.
Includes RTG4
cores: PCIE_SERDES_IF, PCIE_SERDES_IF_INIT, NPSS_SERDES_IF,
NPSS_SERDES_IF_INIT
For SERDES
cores without auto initialization, including PCIe, copy
updated SERDES_*_init_abc.txt program into CoreABC.
Note: The Libero SoC v2025.1 design flow
will error out during netlist Compile if older core versions are
detected.
For new designs, use Libero
SoC v2025.1 and the latest RTG4FCCCECALIB v2.2.100, FDDR v2.0.200, and
SerDes v2.0.200 cores.
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
