24.8.8 Status
Name: | STATUS |
Offset: | 0x10 |
Reset: | 0x0000 |
Property: | - |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
SYNCBUSY | |||||||||
Access | R/W | ||||||||
Reset | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
BUFOVF | FERR | PERR | |||||||
Access | R/W | R/W | R/W | ||||||
Reset | 0 | 0 | 0 |
Bit 15 – SYNCBUSY Synchronization Busy
This bit is cleared when the synchronization of registers between the clock domains is complete.
This bit is set when the synchronization of registers between clock domains is started.
Bit 2 – BUFOVF Buffer Overflow
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set when a buffer overflow condition is detected. A buffer overflow occurs when the receive buffer is full, there is a new character waiting in the receive shift register and a new start bit is detected.
Value | Description |
---|---|
0 | Writing '0' to this bit has no effect. |
1 | Writing '1' to this bit will clear it. |
Bit 1 – FERR Frame Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if the received character had a frame error, i.e., when the first stop bit is zero.
Value | Description |
---|---|
0 | Writing '0' to this bit has no effect. |
1 | Writing '1' to this bit will clear it. |
Bit 0 – PERR Parity Error
Reading this bit before reading the Data register will indicate the error status of the next character to be read.
This bit is cleared by writing '1' to the bit or by disabling the receiver.
This bit is set if parity checking is enabled (CTRLA.FORM is 0x1) and a parity error is detected.
Value | Description |
---|---|
0 | Writing '0' to this bit has no effect. |
1 | Writing '1' to this bit will clear it. |