14.3 Block Diagram

The generation of Peripheral Clock signals (GCLK_PERIPHERAL) and the Main Clock (GCLK_MAIN) can be seen in the figure below.

Figure 14-1. Device Clocking Diagram

The GCLK block diagram is shown in the next figure.

Figure 14-2. Generic Clock Controller Block Diagram⁽¹⁾

Note: 1. If GENCTRL.SRC=0x01(GCLKIN), the GCLK_IO is set as an input.

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