20.8.1 Control A

Name: CTRLA
Offset: 0x00
Reset: 0x0000
Property: PAC Write-Protection

Bit 15141312111098 
 CMDEX[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
  CMD[6:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 15:8 – CMDEX[7:0] Command Execution

When this bit group is written to the key value 0xA5, the command written to CMD will be executed. If a value different from the key value is tried, the write will not be performed and the Programming Error bit in the Status register (STATUS.PROGE) will be set. PROGE is also set if a previously written command is not completed yet.

The key value must be written at the same time as CMD. If a command is issued through the APB bus on the same cycle as an AHB bus access, the AHB bus access will be given priority. The command will then be executed when the NVM block and the AHB bus are idle.

INTFLAG.READY must be '1' when the command is issued.

Bit 0 of the CMDEX bit group will read back as '1' until the command is issued.

Note: The NVM Address bit field in the Address register (ADDR.ADDR) uses 16-bit addressing.

Bits 6:0 – CMD[6:0] Command

These bits define the command to be executed when the CMDEX key is written.

CMD[6:0]Group ConfigurationDescription
0x00-0x01-Reserved
0x02ERErase Row - Erases the row addressed by the ADDR register in the NVM main array.
0x03-Reserved
0x04WPWrite Page - Writes the contents of the page buffer to the page addressed by the ADDR register.
0x05EAR

Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the User Configuration Row.

0x06WAP

Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the User Configuration Row.

0x07-0x3F-Reserved
0x40LRLock Region - Locks the region containing the address location in the ADDR register.
0x41URUnlock Region - Unlocks the region containing the address location in the ADDR register.
0x42SPRMSets the Power Reduction Mode.
0x43CPRMClears the Power Reduction Mode.
0x44PBCPage Buffer Clear - Clears the page buffer.
0x45SSBSet Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row.
0x46INVALLInvalidates all cache lines.
0x47-0x7F-Reserved