32.12.3 Digital Frequency Locked Loop (DFLL48M) Characteristics

Table below provides the characteristics of the DFLL48M.

Table 32-45. DFLL48M Characteristics - Closed Loop Mode⁽¹⁾⁽²⁾
Symbol	Parameter	Conditions	Min.	Typ.	Max.	Units
f_OUT	Average Output frequency	f_REF = XOSC32K 32.768 kHz	47	48	49	MHz
f_REF	Reference frequency		0.732	32.768	35.1	kHz
Jitter	Period jitter	f_REF = XOSC32K 32.768 kHz	-	-	0.42	ns
I_DFLL	Power consumption on V_DDIN	f_REF = XOSC32K 32.768 kHz. For SAMD20 revision C devices	-	397	-	μA
I_DFLL	Power consumption on V_DDIN	f_REF = XOSC32K 32.768 kHz. For SAMD20 revision D devices and later.	-	292	-	μA
t_LOCK	Lock time	f_REF = XOSC32K 32.768 kHz  DFLLVAL.COARSE =  DFLL48M COARSE CAL DFLLVAL.FINE = 512  DFLLCTRL.BPLCKC = 1 DFLLCTRL.QLDIS = 0 DFLLCTRL.CCDIS = 1 DFLLMUL.FSTEP = 10	100	200	500	μs
t_LOCK	Lock time	Quick lock disabled,  Chill cycle disabled,  CSTEP = 3, FSTEP = 1,  f_REF = XOSC32K 32.768 kHz	-	600	-	μs

Note:

Refer to the revision C/revision B errata related to the DFLL48M.
All parts are tested in production to be able to use the DFLL as main CPU clock whether in DFLL Closed Loop mode with an external OSC reference or in DFLL Closed Loop mode using the internal OSC8M (Only applicable for revision C).