28.8.2 Reference Control

Name: REFCTRL
Offset: 0x01
Reset: 0x00
Property: Write-Protected

Bit 76543210 
 REFCOMP   REFSEL[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable

The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference.

ValueDescription
0

Reference buffer offset compensation is disabled.

1

Reference buffer offset compensation is enabled.

Bits 3:0 – REFSEL[3:0] Reference Selection

These bits select the reference for the ADC.

Table 28-5. Reference Selection
REFSEL[3:0]NameDescription
0x0INT1V1.0V voltage reference
0x1INTVCC01/1.48 VDDANA
0x2INTVCC11/2 VDDANA (only for VDDANA > 2.0V)
0x3VREFAExternal reference
0x4VREFBExternal reference
0x5-0xFReserved
Note: INT1V is the buffered internal reference of 1.0V, derived from the internal 1.1V bandgap reference.