1.6.1 Operation of Timer0 is Incorrect When FOSC/4 is Used as the Clock Source
Clearing the TMR0 Input Asynchronous Enable (T0ASYNC) bit of the T0CON1 register when Timer0 is configured to use FOSC/4 as its clock source may cause incorrect behavior.
Work around
Ensure that the T0ASYNC bit is set when using FOSC/4 as the clock source.
Affected Silicon Revisions
| A3 | A4 | A6 | |||||
| X | X |