1.4.2 SSPBUF Transmit Shift Register May Be Corrupted Under Certain Conditions

When operating in SPI Slave mode, if the incoming SCK clock signal arrives during any of the conditions below, the SSPBUF transmit shift register may become corrupted. The transmitted slave byte cannot be assured to be correct, and the state of the WCOL bit may or may not indicate a write collision.

These conditions include:
  • A write to an SFR
  • A write to RAM following an SFR read
  • A write to RAM prior to an SFR read

Work around

Method 1 (Interrupt-based using SS):

Connect the SS line to both the SS input and either an INT or IOC pin.
  1. Enable INT or IOC interrupts (interrupt on falling edge, if available; otherwise check that SS = 0 when the interrupt occurs).
  2. Load SSPBUF with the data to be transmitted.
  3. Continue program execution.
  4. When the Interrupt Service Routine (ISR) is invoked, do either of the following:
    • Add a delay that ensures the first SCK clock will be complete.
    • Poll SSPSTAT.BF (while (BF == 0)), and wait for the transmission/reception to complete.

    Once one of these two methods are complete, it is safe to return to program execution.

Method 2 (SS not available):

  1. Load SSPBUF with the data to be transmitted.
  2. Poll SSPSTAT.BF (while (BF == 0)), and wait for the transmission or reception to complete.

Affected Silicon Revisions

A3A4A6
XX