4.1 Global SRAM Variables

The following table provides details about the SRAM variables to handle wM-Bus transmission/reception. The user can access the SRAM variables via the Write SRAM/Register (command ID 0x07) and the Read SRAM/Register (command ID 0x08) SPI commands.

Table 4-1. Global SRAM Variables
SRAM Variable / Element I/O Address Size Description Bit 7 6 5 4 3 2 1 0
g_wmbusCr 0x04D0-0x04D4 5-bytes wM-Bus Control Register Structure Bit 7 6 5 4 3 2 1 0
g_wmbusCr.bValue 0x04D0 1-byte wM-Bus control register — Mode — — RD SD
Read/Write R/W R/W R/W R/W Reserved Reserved R/W R/W

Bit[7:4]: Mode – wM-Bus mode

0 – S1 mode (long preamble)

1 – S2 mode (short preamble)

2 – T1 mode (3-of-6 encoding; meter to other)

3 – T2 mode (Manchester encoding; other to meter)

[4:15] – Reserved

Bit[3:2]: Reserved – Reserved

Bit 1: RD – Receive Buffered Data

Writing a logic one to this bit starts RF telegram reception in the given mode.

Bit is automatically cleared when reception is finished.

Bit 0: SD – Send Buffered Data

Writing a logic one to this bit starts RF telegram transmission of given data in the given mode.

Bit is automatically cleared after finishing the transmission.
g_wmbusCr.bLenth 0x04D1-0x04D2 2-bytes wM-Bus data length register — Length
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bit[15:0]: Length – wM-Bus data length register

TX – Transmission register defines length of raw data to be send from data buffer, value must be written prior setting bit g_wmbusCr.SD

RX – Reception register defines length of complete RX telegram which was received in data buffer

For more details, refer to 4.3.1 Maximum Telegram Length.
0x04D1 1-byte

Bit[7:0]: Length low byte – wM-Bus data length low byte register
0x04D2 1-byte

Bit[15:8]: Length high byte – wM-Bus data length high byte register
g_wmbusCr.bCField 0x04D3 1-byte wM-Bus C-field register — Value
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bit[7:0]: Value – wM-Bus C-field register

According to the EN60870-5-2 standard, the CI-field defines the message type, and send it as second byte of first block of RF telegram. The value must be written prior to setting bit g_wmbusCr.SD. For more details, refer to the EN60870-5-2 Standard.
g_wmbusCr.bCiField 0x04D4 1-byte wM-Bus CI-field register — Value
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Bit[7:0]: Value – wM-Bus CI-field register

According to the EN13757-3 standard, the CI-field defines the protocol type of data, and send it as first byte of second block of RF telegram. The value must be written prior to setting bit g_wmbusCr.SD. For more details, refer to the EN13757-3 Standard.
g_wmbusSr 0x04D5 1-byte wM-Bus Status Register Structure Bit 7 6 5 4 3 2 1 0
g_wmbusSr.bValue 0x04D5 1-byte wM-Bus status register — RxActive TxActive — — BuffOvf rcErr Rec SndC
Read/Write R R Reserved Reserved R R R/W R/W

Bit 7: RxActive – wM-Bus reception ongoing

0 – No ongoing reception

1 – Ongoing reception

Bit 6: TxActive – wM-Bus transmission ongoing

0 – No ongoing transmission

1 – Ongoing transmission

Bit[5:4]: Reserved – Reserved

Bit 3: BuffOvf – wM-Bus RX buffer overflow

0 – No RX buffer overflow is detected

1 – RX buffer overflow is detected and maximum telegram length is exceeded

Bit 2: CrcErr – wM-Bus CRC error

0 – No CRC error is detected

1 – CRC error is detected on received telegram

Bit 1: Rec – wM-Bus data is received

0 – No data are received

1 – Data are received

Bit 0: SndC – Sending of wM-Bus data completed

0 – Sending of data are not completed

1 – Sending of data are completed
g_wmbusDb 0x0328-0x0441 282-bytes wM-Bus Data Buffer Bit 7 6 5 4 3 2 1 0
g_wmbusDb[] 0x0328-0x0441 282-bytes wM-Bus data buffer — Value
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

TX – wM-Bus data buffer

Raw data for transmission must be written prior to setting bit g_wmbusCr.SD

RX – wM-Bus data buffer

Buffer holds complete RX telegram after receiving the data (g_wmbusSr.Rec = 1)

Data byte order – Little Endian (LSB first)