1.1 Half Bridge Mode

In Half Bridge mode, the CWG generates two output signals which are true and inverted versions of the input signal (see Figure 1-1). A dead-band delay is inserted between the two outputs to prevent shoot-through current in power supply applications. In Half Bridge mode, outputs CWGxA and CWGxB are complimentary. The unused outputs CWGxC and CWGxD are copies of outputs CWGxA and CWGxC, respectively. The polarity of each output is controlled by the individual CWG Output Polarity (POLx) bits of the CWGxCON1 register.