3.4.1 VIH and VIL Specifications

The input levels of the device will vary dependent on the mode and voltage of the device. The input voltage thresholds when in Sleep or Idle mode are dependent on the VCC level as shown in Figure 3-5. When in Sleep or Idle mode the TTLenable bit has no effect.

Table 3-6. VIL, VIH on All I/O Interfaces (TTLenable = 0)
Parameter Sym. Min. Typ. Max. Units Conditions
Input Low Voltage VIL -0.5 — 0.5 V When device is active and TTLenable bit in Configuration memory is zero; otherwise, see above.
Input High Voltage VIH 1.5 — VCC + 0.5 V When device is active and TTLenable bit in Configuration memory is zero; otherwise, see above.
Figure 3-5. VIH and VIL in Sleep and Idle Mode