1.1 Pin Diagram and Pin Functions
The following figure illustrates the pin diagram of the TFBGA33.Figure 1-2. Pin Diagram TFBGA33 
| Pin Number | Pin Name | Type | Function | Voltage Domain |
|---|---|---|---|---|
| A1 | VSUB | Analog | GND | VBAT 3.3V |
| A2 | VSSA_LNA | Analog | GND | VCore 1.25V |
| A3 | RFIO | Analog | RF Antenna Pin | VCore 1.25V |
| A4 | VSSA_PA | Analog | GND | VCore 1.25V |
| A5 | VDDA_SYN | Analog | Core Supply 1.25V | VCore 1.25V |
| A6 | GPO0 | Digital | General Purpose Output 0 (Debug/Test) | VBAT 3.3V |
| B1 | VDDA_LNA | Analog | Core Supply 1.25V | VCore 1.25V |
| B4 | VSSA_PLL | Analog | GND | VCore 1.25V |
| B5 | VSSA_SYN | Analog | GND | VCore 1.25V |
| B6 | VDDA_PLL | Analog | Core Supply 1.25V | VCore 1.25V |
| C1 | XTAL_N | Analog | 48 MHz Crystal Oscillator Negative Port, Gate Contact | — |
| C3 | SPI_MOSI | Digital | SPI Host Out Target In | VBAT 3.3V |
| C4 | SPI_CE | Digital | SPI Chip Select (Active-high) | VBAT 3.3V |
| C5 | GPO1(1) | Digital | General Purpose Output 1 (Debug/Test) | VBAT 3.3V |
| C6 | VDDD1 | Digital | Core Supply 1.25V | VCore 1.25V |
| D1 | XTAL_P | Analog | 48 MHz Crystal Oscillator Positive Port, Drain Contact | — |
| D2 | SPI_CLK | Digital | SPI Clock Input | VBAT 3.3V |
| D3 | SPI_MISO | Digital | SPI Host In Target Out | VBAT 3.3V |
| D4 | N_RST | Digital | Chip Reset (Active-low) | VBAT 3.3V |
| D5 | MST_CLK | Digital | Server Clock Output (default 4 MHz) | VBAT 3.3V |
| D6 | VSSD1 | Digital | GND | VCore 1.25V |
| E1 | VSSA_ADC | Analog | GND | VCore 1.25V |
| E2 | IRQ | Digital | Interrupt Request Output | VBAT 3.3V |
| E3 | TEST_EN(2) | Digital | Test Mode Enable (Active-high) – Connect to GND in Application | VBAT 3.3V |
| E4 | VSS_IO | Digital | GND | VBAT 3.3V |
| E5 | GPO2(1) | Digital | General Purpose Output 2 (Debug/Test) | VBAT 3.3V |
| E6 | GPO3(1) | Digital | General Purpose Output 3 (Debug/Test) | VBAT 3.3V |
| F1 | ATEST | Analog | Analog Test – Open in Application | VCore 1.25V |
| F2 | VDDA_ADC | Analog | Core Supply 1.25V | VCore 1.25V |
| F3 | VDDD2 | Digital | Core Supply 1.25V | VCore 1.25V |
| F4 | VSSD2 | Digital | GND | VCore 1.25V |
| F5 | VDD_IO | Digital | I/O Power Supply 3.3V | VBAT 3.3V |
| F6 | GPO4 | Digital | General Purpose Output 4 (Debug/Test) | VBAT 3.3V |
Note:
- The GPO0 and GPO4 pins are used for testing and debug purposes only and are not intended for general use in an application.
- The TEST_EN (E3) pin is used only for device testing and must be connected to GND for a communication or distance-bounding application.