1.1 Pin Diagram and Pin Functions

The following figure illustrates the pin diagram of the TFBGA33.
Figure 1-2. Pin Diagram TFBGA33
Table 1-2. Pin Description
Pin NumberPin NameTypeFunctionVoltage Domain
A1VSUBAnalogGNDVBAT 3.3V
A2VSSA_LNAAnalogGNDVCore 1.25V
A3RFIOAnalogRF Antenna PinVCore 1.25V
A4VSSA_PAAnalogGNDVCore 1.25V
A5VDDA_SYNAnalogCore Supply 1.25VVCore 1.25V
A6GPO0DigitalGeneral Purpose Output 0 (Debug/Test)VBAT 3.3V
B1VDDA_LNAAnalogCore Supply 1.25VVCore 1.25V
B4VSSA_PLLAnalogGNDVCore 1.25V
B5VSSA_SYNAnalogGNDVCore 1.25V
B6VDDA_PLLAnalogCore Supply 1.25VVCore 1.25V
C1XTAL_NAnalog48 MHz Crystal Oscillator Negative Port, Gate Contact—
C3SPI_MOSIDigitalSPI Host Out Target InVBAT 3.3V
C4SPI_CEDigitalSPI Chip Select (Active-high)VBAT 3.3V
C5GPO1(1)DigitalGeneral Purpose Output 1 (Debug/Test)VBAT 3.3V
C6VDDD1DigitalCore Supply 1.25VVCore 1.25V
D1XTAL_PAnalog48 MHz Crystal Oscillator Positive Port, Drain Contact—
D2SPI_CLKDigitalSPI Clock InputVBAT 3.3V
D3SPI_MISODigitalSPI Host In Target OutVBAT 3.3V
D4N_RSTDigitalChip Reset (Active-low)VBAT 3.3V
D5MST_CLKDigitalServer Clock Output (default 4 MHz)VBAT 3.3V
D6VSSD1DigitalGNDVCore 1.25V
E1VSSA_ADCAnalogGNDVCore 1.25V
E2IRQDigitalInterrupt Request OutputVBAT 3.3V
E3TEST_EN(2)DigitalTest Mode Enable (Active-high) – Connect to GND in ApplicationVBAT 3.3V
E4VSS_IODigitalGNDVBAT 3.3V
E5GPO2(1)DigitalGeneral Purpose Output 2 (Debug/Test)VBAT 3.3V
E6GPO3(1)DigitalGeneral Purpose Output 3 (Debug/Test)VBAT 3.3V
F1ATESTAnalogAnalog Test – Open in ApplicationVCore 1.25V
F2VDDA_ADCAnalogCore Supply 1.25VVCore 1.25V
F3VDDD2DigitalCore Supply 1.25VVCore 1.25V
F4VSSD2DigitalGNDVCore 1.25V
F5VDD_IODigitalI/O Power Supply 3.3VVBAT 3.3V
F6GPO4DigitalGeneral Purpose Output 4 (Debug/Test)VBAT 3.3V
Note:
  1. The GPO0 and GPO4 pins are used for testing and debug purposes only and are not intended for general use in an application.
  2. The TEST_EN (E3) pin is used only for device testing and must be connected to GND for a communication or distance-bounding application.