3.4.1 Debug JTAG
A 10-pin JTAG header (J18) is provided on the SAMA5D2-ICP board to facilitate software development and debug by using various JTAG emulators. The interface signals have a voltage level of 3.3V.
When connecting to J18 using a SAM-ICE, a J32 Probe device or a Segger J-Link debugger, use a standard 50 mil pitch, 10-pin IDC cable such as Samtec’s FFSD-05-S-06.00-01-N or FFSD-05-D-04.00-01-N.
All debuggers mentioned above feature 100 mil, 20-pin connectors, so an adapter must be used. Several adapters are available, including ATATMEL-ICE-ADPT and AC102015. Make sure to use a 10-pin cable as described in the above paragraph (note that pin 1 on one end connects to pin 1 at the other end, and so on). The cable delivered with ATATMEL-ICE-ADAPT is specifically designed to work with ATMEL-ICE and will not work with a SAM-ICE, J32 Probe or Segger J-Link debugger.
The location of the JTAG connector is shown in the picture below.
The table below describes the pin assignment of JTAG connector J18.
| Pin No | Mnemonic | Signal Description |
|---|---|---|
| 1 | VTref. 3.3V power | Target reference voltage (main 3.3V) |
| 2 | TMS (Test Mode Select) | JTAG mode set input into target CPU |
| 3 | GND | Common ground |
| 4 | TCK Test clock - Output timing signal, for synchronizing test logic and control register access | JTAG clock signal into target CPU |
| 5 | GND | Common ground |
| 6 | JTAG TDO (Test Data Output) - Serial data input from the target | JTAG data output from target CPU |
| 7 | RTCK - Input Return test clock signal from the target | Some targets with a system clock that is too slow must synchronize the JTAG inputs to internal clocks. In the present case, such synchronization is unneeded and TCK merely looped back into RTCK. |
| 8 | TDI (Test Data Input) - Serial data output line, sampled on the rising edge of the TCK signal | JTAG data input into target CPU |
| 9 | GND | Common ground |
| 10 | nSRST RESET | Active-low reset signal. Target CPU reset signal. |