3.1.2 Low-Voltage Programming (LVP) Mode

The LVP mode allows the devices to be programmed using VDD only, without high voltage. When the LVP bit in the Configuration Word 4 register is set to ‘1’, the Low-Voltage ICSP Programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the High-Voltage Entry mode.

Entry into the Low-Voltage ICSP Program/Verify mode requires the following steps:
  1. MCLR is brought to VIL.
  2. A 32-bit key sequence is presented on ICSPDAT and clocked by ICSPCLK. The Least Significant bit (LSb) of the pattern is a ‘don’t care X’. The Program/Verify mode entry pattern detect hardware verifies only the first 31 bits of the sequence and the last clock is required before the pattern detect goes active.

The key sequence is a specific 32-bit pattern, ‘32’h4d434850’ (more easily remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The MSb of the Most Significant Byte (MSB) must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. For LVP timing, see Figure 3-3 and Figure 3-4.

Figure 3-3. LVP Entry (Powered)
Figure 3-4. LVP Entry (Powering Up)
Important:

To enter LVP mode, the MSb of the Most Significant nibble must be shifted in first. This differs from entering the key sequence on some other device families.