25.3.2.2.1 The Fractional Baud-Rate Generator

In modes where the USART does not use the XCK input as a clock source, the fractional Baud-Rate Generator is used to generate the clock. The baud rate is given in bits per second (bps) and is configured by writing the USARTn.BAUD register. The baud rate (f_BAUD) is generated by dividing the peripheral clock (f_{CLK_PER}) by a division factor determined by the BAUD register.

The fractional Baud-Rate Generator includes hardware that accommodates cases where f_{CLK_PER} is not divisible by f_BAUD. Normally, this situation would lead to a rounding error. The fractional Baud-Rate Generator expects the BAUD register to contain the desired division factor left-shifted by six bits, as implemented by the equations in Table 25-1. The six least significant bits will then hold the fractional part of the desired divisor. This fractional part of the BAUD register is used to dynamically adjust f_BAUD to achieve a closer approximation of the desired baud rate.

Since the baud rate cannot be higher than f_{CLK_PER}, the integer part of the BAUD register must be at least 1. Because the result is left-shifted by six bits, the corresponding minimum value of the BAUD register is 64. The valid range is, therefore, 64 to 65,535.

In Synchronous mode, only the 10-bit integer part of the BAUD register (BAUD[15:6]) determines the baud rate; therefore the fractional part (BAUD[5:0]) must be written as zero.

The table below lists equations for translating baud rates into input values for the BAUD register. The equations take fractional interpretation into consideration, so the BAUD values calculated with these equations can be written directly to USARTn.BAUD without any additional scaling.

Table 25-1. Equations for Calculating Baud Rate Register Setting
Operating Mode	Conditions	Baud Rate (Bits Per Second)	USART.BAUD Register Value Calculation
Asynchronous	$f_{B A U D} \leq \frac{f_{C L K_P E R}}{S}$ $U S A R T . B A U D \geq 64$	$f_{B A U D} = \frac{64 \times f_{C L K_P E R}}{S \times B A U D}$	$B A U D = \frac{64 \times f_{C L K_P E R}}{S \times f_{B A U D}}$
Synchronous Host	$f_{B A U D} \leq \frac{f_{C L K_P E R}}{S}$ $U S A R T . B A U D \geq 64$	$f_{B A U D} = \frac{f_{C L K_P E R}}{S \times B A U D [15 : 6]}$	$B A U D [15 : 6] = \frac{f_{C L K_P E R}}{S \times f_{B A U D}}$

S is the number of samples per bit

Asynchronous Normal mode: S = 16
Asynchronous Double-Speed mode: S = 8
Synchronous mode: S = 2