25.4.3 Transmit Data Register Low Byte
The data written to this register is automatically loaded into the TX Buffer and then into the dedicated shift register. The shift register outputs each bit serially to the TXD pin.
When using a 9-bit frame size, the ninth bit (MSb) must be written to the Transmit Data Register High Byte (USARTn.TXDATAH). In that case, the buffer shifts data either when the Transmit Data Register Low Byte (USARTn.TXDATAL) or the Transmit Data Register High Byte (USARTn.TXDATAH) is written, depending on the configuration. The register thatdoes not cause data to be shifted must be written first to allow both registers to be written before shifting occurs.
When the Character Size (CHSIZE) bit field in the Control C (USARTn.CTRLC) register is configured to 9-bit (low byte first), writing to the Transmit Data Register High Byte shifts the transmit buffer; otherwise, writing to the Transmit Data Register Low Byte shifts the buffer.
This register may be written only when the Data Register Empty Interrupt Flag (DREIF) in the Status (USARTn.STATUS) register is set.
| Name: | TXDATAL |
| Offset: | 0x02 |
| Reset: | 0x00 |
| Property: | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DATA[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |