1 Silicon Issue Summary

In this table and in subsequent sections, the following applies:
  • “X” means the silicon revision is affected by the erratum.
  • “–” means the silicon revision is not affected by the erratum.
Table 1-1. Silicon Issue Summary
ModuleErratumAffected Silicon Revisions

A0

A0-D1G

A0-D2G

A1

A1-D1G

A1-D2G

A1-D5M

ROM CodeThe device does not boot on some QSPI memoriesX–
Card Detect for SDMMC boot limited to PIOA pinsXX
LCDCLCDC Register Write Protection status incorrect on some registersXX
PMCPLL_INT Interrupt Enable has no effectXX
Delay to first establish PCKXX
PCK and GCLK Ready status issueXX
Processor (CPU_CLK) and main system bus clock (MCK) source selectionXX
RSTCRSTC_SR.RSTTYP not showing GENERAL_RSTXX
SMCRegister Write Protection not effective on SMC_OCMS registerXX
AESSPLIP mode does not work with some header sizesXX
QSPIQSPI read with XDMA limited performanceXX
MCANMCAN_TSU_TSCFG reset after readXX
MCAN_TSU_TSS1 not reset after a MCAN_TSU_TSx readXX
MCAN_TSU_ATB read resets the timebase valueXX
Debug message handling state machine not reset to Idle state when CCCR.INIT is setXX