4.2 Delay to first establish PCK

When enabling a PCK after a reset, the delay before establishing the PCK with the correct frequency is 255 cycles of the PCK source clock. Once this delay has elapsed, and as long as the core reset is not asserted, there is no more additional delay when disabling/enabling the PCK.

Work Around

None

Affected Silicon Revisions

A0

A0-D1G

A0-D2G

A1

A1-D1G

A1-D2G

A1-D5M

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