4.3.2.1 Data Input and Output Frames

DATA Zero: If SDA is low and stable while SCL goes from low to high to low, a zero bit is transferred on the bus. SDA can change while SCL is low.
DATA One: If SDA is high and stable while SCL goes from low to high to low, a one bit is transferred on the bus. SDA can change while SCL is low.
Figure 4-12. Data Bit Transfer on the I²C Interface
Start Condition: A high-to-low transition of SDA with SCL high is a Start condition that must precede all commands.
Stop Condition: A low-to-high transition of SDA with SCL high is a Stop condition. After this condition is received by the device, the current I/O transaction ends. On input, if the device has sufficient bytes to execute a command, the device transitions to the busy state and begins execution. The Stop condition must always be sent at the end of any packet sent to the device.
Figure 4-13. Start and Stop Conditions on the I²C Interface
Acknowledge (ACK): On the ninth clock cycle after every address or data byte is transferred, the receiver will pull the SDA pin low to acknowledge proper reception of the byte.
Not Acknowledge (NACK): Alternatively, on the ninth clock cycle after every address or data byte is transferred, the receiver can leave the SDA pin high to indicate that there was a problem with the reception of the byte or that this byte completes the group transfer.
Figure 4-14. NACK and ACK Conditions on the I²C Interface

Multiple SHA104 devices can easily share the same I²C interface signals if the Device_Address byte in the Configuration zone is programmed differently for each device on the bus. All seven bits of the device address are programmable; therefore, the SHA104-TFLXAUTH can also share the I²C interface with any I²C device, including any Serial EEPROM.