12.3.7.2 Condition Clearing
The CFD condition is cleared after a Reset, the monitored source starts toggling again, or the
CFD flag in the Main Clock Interrupt Flags (CLKCTRL.MCLKINTFLAGS) register
is set. Note that as long as the failure condition is met, the interrupt
will trigger every ten OSC32K cycles. If these repeated interrupts are not
desired, write a ‘0
’ to the Clock Failure Detection (CFD)
interrupt enable bit in the Main Clock Interrupt Control (CLKCTRL.MCLKCTRL)
register. If it is the main clock that is being monitored, changing back to
the default start-up clock will make the main clock start toggling again,
clearing the condition.