8.8.2.4 System Configuration 0

The default value given in this fuse description is the factory-programmed value and may not be mistaken for the Reset value.

Name: SYSCFG0
Offset: 0x05
Reset: 0xC0
Property: -

Bit 76543210 
 CRCSRC[1:0]CRCSEL RSTPINCFG  EESAVE 
Access RRRRR 
Reset 11000 

Bits 7:6 – CRCSRC[1:0] CRC Source

This bit field controls which section of the Flash will be checked by the CRCSCAN peripheral during the Reset initialization. Refer to the CRCSCAN section for more information about the functionality.
ValueNameDescription
0x0 FLASH CRC of full Flash (boot, application code, and application data)
0x1 BOOT CRC of the Boot section
0x2 BOOTAPP CRC of the Application code and Boot sections
0x3 NOCRC No CRC

Bit 5 – CRCSEL CRC Mode Selection

This bit controls the type of CRC performed by the CRCSCAN peripheral. Refer to the CRCSCAN section for more information about the functionality.
ValueNameDescription
0 CRC16 CRC-16-CCITT
1 CRC32 CRC-32 (IEEE 802.3)

Bit 3 – RSTPINCFG Reset Pin Configuration at Start-Up

This bit controls the pin configuration for the Reset pin.
ValueNameDescription
0 INPUT No external reset
1 RESET External reset with pull-up enabled on PF6

Bit 0 – EESAVE EEPROM Saved During Chip Erase

This bit controls if the EEPROM will be erased or saved during a chip erase.
ValueNameDescription
0 DISABLE EEPROM is erased during a chip erase
1 ENABLE EEPROM is saved during a chip erase regardless of whether the device is locked or not