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AVR® DB Family
Introduction
AVR® DB Family Overview
1 Memory Overview
2 Peripheral Overview
Features
1 Block Diagram
2 Pinout
2.1 28-pin SSOP, SOIC and SPDIP
2.2 32-pin VQFN and TQFP
2.3 48-pin VQFN and TQFP
3 I/O Multiplexing and Considerations
3.1 I/O Multiplexing
4 Hardware Guidelines
4.1 General Guidelines
4.2 Connection for Power Supply
4.3 Connection for RESET
4.4 Connection for UPDI Programming
4.5 Connecting External Crystal Oscillators
4.6 Connection for External Voltage Reference
5 Power Supply
5.1 Power Domains
5.2 Voltage Regulator
5.3 Power-Up
6 Conventions
6.1 Numerical Notation
6.2 Memory Size and Type
6.3 Frequency and Time
6.4 Registers and Bits
6.5 ADC Parameter Definitions
7 AVR® CPU
7.1 Features
7.2 Overview
7.3 Architecture
7.4 Functional Description
7.5 Register Summary
7.6 Register Description
8 Memories
8.1 Overview
8.2 Memory Map
8.3 In-System Reprogrammable Flash Program Memory
8.4 SRAM Data Memory
8.5 EEPROM Data Memory
8.6 SIGROW - Signature Row
8.7 USERROW - User Row
8.8 FUSE - Configuration and User Fuses
8.9 LOCK - Memory Sections Access Protection
8.10 I/O Memory
9 GPR - General Purpose Registers
9.1 Register Summary
9.2 Register Description
10 Peripherals and Architecture
10.1 Peripheral Address Map
10.2 Interrupt Vector Mapping
10.3 SYSCFG - System Configuration
11 NVMCTRL - Nonvolatile Memory Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 CLKCTRL - Clock Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 SLPCTRL - Sleep Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 RSTCTRL - Reset Controller
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 CPUINT - CPU Interrupt Controller
15.1 Features
15.2 Overview
15.3 Functional Description
15.4 Register Summary
15.5 Register Description
16 EVSYS - Event System
16.1 Features
16.2 Overview
16.3 Functional Description
16.4 Register Summary
16.5 Register Description
17 PORTMUX - Port Multiplexer
17.1 Overview
17.2 Register Summary
17.3 Register Description
18 PORT - I/O Pin Configuration
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary - PORTx
18.5 Register Description - PORTx
18.6 Register Summary - VPORTx
18.7 Register Description - VPORTx
19 MVIO - Multi-Voltage I/O
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary
19.5 Register Description
20 BOD - Brown-out Detector
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary
20.5 Register Description
21 VREF - Voltage Reference
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary
21.5 Register Description
22 WDT - Watchdog Timer
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary
22.5 Register Description
23 TCA - 16-bit Timer/Counter Type A
23.1 Features
23.2 Overview
23.3 Functional Description
23.4 Register Summary - Normal Mode
23.5 Register Description - Normal Mode
23.6 Register Summary - Split Mode
23.7 Register Description - Split Mode
24 TCB - 16-Bit Timer/Counter Type B
24.1 Features
24.2 Overview
24.3 Functional Description
24.4 Register Summary
24.5 Register Description
25 TCD - 12-Bit Timer/Counter Type D
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 RTC - Real-Time Counter
26.1 Features
26.2 Overview
26.3 Clocks
26.4 RTC Functional Description
26.5 PIT Functional Description
26.6 Crystal Error Correction
26.7 Events
26.8 Interrupts
26.9 Sleep Mode Operation
26.10 Synchronization
26.11 Debug Operation
26.12 Register Summary
26.13 Register Description
27 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary
27.5 Register Description
28 SPI - Serial Peripheral Interface
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 TWI - Two-Wire Interface
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 CRCSCAN - Cyclic Redundancy Check Memory Scan
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary
30.5 Register Description
31 CCL - Configurable Custom Logic
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary
31.5 Register Description
32 AC - Analog Comparator
32.1 Features
32.2 Overview
32.3 Functional Description
32.4 Register Summary
32.5 Register Description
33 ADC - Analog-to-Digital Converter
33.1 Features
33.2 Overview
33.3 Functional Description
33.4 Register Summary
33.5 Register Description
34 DAC - Digital-to-Analog Converter
34.1 Features
34.2 Overview
34.3 Functional Description
34.4 Register Summary
34.5 Register Description
35 OPAMP - Analog Signal Conditioning
35.1 Features
35.2 Overview
35.3 Functional Description
35.4 Register Summary
35.5 Register Description
36 ZCD - Zero-Cross Detector
36.1 Features
36.2 Overview
36.3 Functional Description
36.4 Register Summary
36.5 Register Description
37 UPDI - Unified Program and Debug Interface
37.1 Features
37.2 Overview
37.3 Functional Description
37.4 Register Summary
37.5 Register Description
38 Instruction Set Summary
39 Electrical Characteristics
39.1 Disclaimer
39.2 Absolute Maximum Ratings
39.3 Standard Operating Conditions
39.4 Supply Voltage
39.5 Power Consumption
39.6 Peripherals Power Consumption
39.7 I/O Pins
39.8 Memory Programming Specifications
39.9 Thermal Specifications
39.10 CLKCTRL
39.11 RSTCTRL
39.12 VREF
39.13 TCD
39.14 USART
39.15 SPI - Timing Characteristics
39.16 TWI
39.17 AC
39.18 ADC
39.19 DAC
39.20 OPAMP
39.21 ZCD
39.22 UPDI
40 Characteristics Graphs
40.1 Power Consumption
40.2 Peripheral Power Consumption
40.3 CLKCTRL
40.4 Reset Controller
40.5 I/O Pins
40.6 VREF
40.7 ADC
40.8 Temperature Sensor
40.9 AC
40.10 DAC
40.11 OPAMP
40.12 ZCD
41 Ordering Information
42 Package Drawings
42.1 Online Package Drawings
42.2 Package Marking Information
42.3 28-Pin SPDIP
42.4 28-Pin SOIC
42.5 28-Pin SSOP
42.6 32-Pin VQFN
42.7 32-Pin VQFN Wettable Flanks
42.8 32-Pin TQFP
42.9 48-Pin VQFN
42.10 48-Pin VQFN Wettable Flanks
42.11 48-Pin TQFP
43 Data Sheet Revision History
43.1 Rev. B - 12/2024
43.2 Rev.A - 02/2021
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