43.1 Rev. B - 12/2024

Section	Description
Document	Editorial updates Updated terminology: Master is replaced by host Slave is replaced by client
Features	The Flash write/erase endurance is 1,000 cycles
Hardware Guidelines	Improved the Connection for Power Supply section (decoupling capacitors) Added a new connector for UPDI to Connection for UPDI Programming section Added series resistor to the Connection for XTAL32K section
AVR® CPU	Added single cycle ALU operation to “Instruction Execution Timing” More detailed description of the CCP section
Memories	New version of the memory map image Added start address to the SRAM table
NVMCTRL	Updated block diagram Expanded several sections of the Flash section Expanded description of the FLMAP bit field in the CTRLB register Expanded description of the ERROR bit field in the STATUS register
CLKCTRL	Update made to the block diagram Added missing Interrupts section Aligned CLKCTRL with the Electrical Characteristics section Corrected a name in the PDIV bit field in the MCLKCTRLB register Added a name column in the SEL bit field in the XOSC32KCTRLA register
SLPCTRL	Expanded the table in the Voltage Regulator Configuration section Updates made to the several tables in the Sleep Modes section Update made to the PMODE bit field description in the VREGCTRL register
RSTCTRL	A clarification is made to the Initialization section A clarification is made to the External Reset section The table in the Domains Affected by Reset section is expanded
CPUINT	Clarification made to step 4 in the Initialization section The figure in the Round Robin Scheduling section is improved The IVSEL bit field description in the CTRLA register is improved
EVSYS	Clarification made to the Overview section Clarification made to the main description in the CHANNELn register
PORT	Clarification of TTL compatibility added to the Pin Configuration section Clarifications made to the Multi-Pin Configuration section Clarification made to CLK_PER activity in Sleep mode in the Asynchronous Sensing Port Properties Several clarifications made to the PINCONFIG register Several clarifications made to the PINnCTRL register
MVIO	Update made to the Power Sequencing section
BOD	Clarification made to BODLEVEL0 in the CTRLB register Corrected register name to VLMCTRLA
VREF	Clarification made to Initialization regarding noise
WDT	Clarification made to the STATUS register
TCA	Clarification made to the Overview section Note added to the Waveform Generation section The Split Mode Overview section is expanded Update made to the CMPnEN bit field description of the CTRLB register
TCB	Clarification made to the Initialization section Clarification made to the CCMPEN bit of the CTRLB register
TCD	Added formula and a figure to the Programmable Output Events section Fault is replaced by Fault condition in the entire section Clarifications are made to all bit descriptions of the FAULTCTRL register
RTC	Clarification made to the: CTRLA register CNTx register PERx register COMPx register PITCTRLA register about checking the CNTBUSY flag in the STATUS or PITSTATUS register to check if the register is ready to be updated.
USART	Correction made to the block diagram in the IRCOM Mode of Operation section (Decoded/Encoded TxD) Corrected Reset value for the STATUS register Clarification made to the WFB bit in the STATUS register Correction made to the IREI bit of the EVCTRL register (enabled/disabled was swapped)
SPI	Some text related to timing was removed from the Client Mode section Clarifications have been made to functionality and timing requirements in the Client Mode - Buffer Mode section A clarification has been made to the Interrupt Flag bit in INTFLAGS - Normal Mode register
TWI	Clarifications have been made to the TIMEOUT bit field of the MCTRLA register A clarification has been made to the FLUSH bit of the MCTRLB register A clarification has been made to the BUSSTATE bit field of the MSTATUS register
CCL	Clarifications have been made to the Gated D Flip-Flop and characteristics tables in the Sequencer Logic section Updated the figure in the Clock Source Settings section A clarification has been made to the CLKSRC bit field of the LUTnCTRLA register Clarifications have been made to the TRUTH bit field of the TRUTHn register
AC	An update has been made to the block diagram in the Window Mode section Correction has been made to the INTMODE bit field of the INTCTRL register (swapped NEGEDGE and POSEDGE)
ADC	Clarifications have been made to the Features section Clarifications have been made to the Clock Generation section Clarifications have been made to the formulas in the Conversion Results section Clarifications have been made to the code snippet in the Temperature Measurement section Clarifications have been made to the description of inputs in the MUXPOS bit field of the MUXPOS register
DAC	A clarification has been made to the Features section The block diagram has been updated (Block Diagram section) Updates have been made to the Operation section; several sections have been changed (including headings) A clarification has been made to the description of the DATA register
OPAMP	Clarifications have been made to the Input Voltage Range (and Bias Current) section Clarifications have been made to the Offset Calibration section Clarifications have been made to most tables in the Application Usage section
UPDI	New section added to the Overview section: Addressing the Program Memory Space A clarification has been made to the Chip Erase section
Electrical Characteristics	The entire section is updated in new format All sections are updated with new numbers as part of the Complete Data Sheet release Most sections have updates to the tables
Characteristics Graphs	Section is renamed to Characteristics Graphs for clarity (old title was Typical Characteristics) Characteristics graphs added for the device and relevant peripherals OPAMP plots are reformatted into the new standard
Ordering Information	Added note regarding automotive parts
Package Drawings	Added Package Marking Information section Update to 32-pin VQFN package drawing Added 32-pin VQFN wettable flanks drawing Update to 32-pin TQFP package drawing Update to 48-pin VQFN package drawing Added 48-pin VQFN wettable flanks drawing Update to 64-pin VQFN package drawing Added 64-pin VQFN wettable flanks drawing Update to 64-pin TQFP package drawing
Data Sheet Revision History	Added Revision B section

Document

Editorial updates
Updated terminology:
- Master is replaced by host
- Slave is replaced by client

Features

The Flash write/erase endurance is 1,000 cycles

Hardware Guidelines

Improved the Connection for Power Supply section (decoupling capacitors)
Added a new connector for UPDI to Connection for UPDI Programming section
Added series resistor to the Connection for XTAL32K section

AVR® CPU

Added single cycle ALU operation to “Instruction Execution Timing”
More detailed description of the CCP section

Memories

New version of the memory map image
Added start address to the SRAM table

NVMCTRL

Updated block diagram
Expanded several sections of the Flash section
Expanded description of the FLMAP bit field in the CTRLB register
Expanded description of the ERROR bit field in the STATUS register

CLKCTRL

Update made to the block diagram
Added missing Interrupts section
Aligned CLKCTRL with the Electrical Characteristics section
Corrected a name in the PDIV bit field in the MCLKCTRLB register
Added a name column in the SEL bit field in the XOSC32KCTRLA register

SLPCTRL

Expanded the table in the Voltage Regulator Configuration section
Updates made to the several tables in the Sleep Modes section
Update made to the PMODE bit field description in the VREGCTRL register

RSTCTRL

A clarification is made to the Initialization section
A clarification is made to the External Reset section
The table in the Domains Affected by Reset section is expanded

CPUINT

Clarification made to step 4 in the Initialization section
The figure in the Round Robin Scheduling section is improved
The IVSEL bit field description in the CTRLA register is improved

EVSYS

Clarification made to the Overview section
Clarification made to the main description in the CHANNELn register

PORT

Clarification of TTL compatibility added to the Pin Configuration section
Clarifications made to the Multi-Pin Configuration section
Clarification made to CLK_PER activity in Sleep mode in the Asynchronous Sensing Port Properties
Several clarifications made to the PINCONFIG register
Several clarifications made to the PINnCTRL register

MVIO

Update made to the Power Sequencing section

BOD

Clarification made to BODLEVEL0 in the CTRLB register
Corrected register name to VLMCTRLA

VREF

Clarification made to Initialization regarding noise

WDT

Clarification made to the STATUS register

TCA

Clarification made to the Overview section
Note added to the Waveform Generation section
The Split Mode Overview section is expanded
Update made to the CMPnEN bit field description of the CTRLB register

TCB

Clarification made to the Initialization section
Clarification made to the CCMPEN bit of the CTRLB register

TCD

Added formula and a figure to the Programmable Output Events section
Fault is replaced by Fault condition in the entire section
Clarifications are made to all bit descriptions of the FAULTCTRL register

RTC

Clarification made to the:
- CTRLA register
- CNTx register
- PERx register
- COMPx register
- PITCTRLA register
about checking the CNTBUSY flag in the STATUS or PITSTATUS register to check if the register is ready to be updated.

USART

Correction made to the block diagram in the IRCOM Mode of Operation section (Decoded/Encoded TxD)
Corrected Reset value for the STATUS register
Clarification made to the WFB bit in the STATUS register
Correction made to the IREI bit of the EVCTRL register (enabled/disabled was swapped)

SPI

Some text related to timing was removed from the Client Mode section
Clarifications have been made to functionality and timing requirements in the Client Mode - Buffer Mode section
A clarification has been made to the Interrupt Flag bit in INTFLAGS - Normal Mode register

TWI

Clarifications have been made to the TIMEOUT bit field of the MCTRLA register
A clarification has been made to the FLUSH bit of the MCTRLB register
A clarification has been made to the BUSSTATE bit field of the MSTATUS register

CCL

Clarifications have been made to the Gated D Flip-Flop and characteristics tables in the Sequencer Logic section
Updated the figure in the Clock Source Settings section
A clarification has been made to the CLKSRC bit field of the LUTnCTRLA register
Clarifications have been made to the TRUTH bit field of the TRUTHn register

AC

An update has been made to the block diagram in the Window Mode section
Correction has been made to the INTMODE bit field of the INTCTRL register (swapped NEGEDGE and POSEDGE)

ADC

Clarifications have been made to the Features section
Clarifications have been made to the Clock Generation section
Clarifications have been made to the formulas in the Conversion Results section
Clarifications have been made to the code snippet in the Temperature Measurement section
Clarifications have been made to the description of inputs in the MUXPOS bit field of the MUXPOS register

DAC

A clarification has been made to the Features section
The block diagram has been updated (Block Diagram section)
Updates have been made to the Operation section; several sections have been changed (including headings)
A clarification has been made to the description of the DATA register

OPAMP

Clarifications have been made to the Input Voltage Range (and Bias Current) section
Clarifications have been made to the Offset Calibration section
Clarifications have been made to most tables in the Application Usage section

UPDI

New section added to the Overview section: Addressing the Program Memory Space
A clarification has been made to the Chip Erase section

Electrical Characteristics

The entire section is updated in new format
All sections are updated with new numbers as part of the Complete Data Sheet release
Most sections have updates to the tables

Characteristics Graphs

Section is renamed to Characteristics Graphs for clarity (old title was Typical Characteristics)
Characteristics graphs added for the device and relevant peripherals
OPAMP plots are reformatted into the new standard

Ordering Information

Added note regarding automotive parts

Package Drawings

Added Package Marking Information section
Update to 32-pin VQFN package drawing
Added 32-pin VQFN wettable flanks drawing
Update to 32-pin TQFP package drawing
Update to 48-pin VQFN package drawing
Added 48-pin VQFN wettable flanks drawing
Update to 64-pin VQFN package drawing
Added 64-pin VQFN wettable flanks drawing
Update to 64-pin TQFP package drawing

Data Sheet Revision History

Added Revision B section