36.3.2.2 ZCD Logic Output

The STATE flag in the ZCDn.STATUS register indicates whether the input signal is above or below the reference voltage, Z_CPINV. By default, the STATE flag is ‘1’ when the input signal is above the reference voltage and ‘0’ when the input signal is below the reference voltage. Writing the INVERT bit to ‘1’ in the ZCDn.CTRLA register can reverse the STATE flag polarity. The INVERT bit will also affect ZCD interrupt polarity.