24.3.4 Events

The TCB can generate the events described in the following table:

Table 24-3. Event Generators in TCB
Generator Name		Description	Event Type	Generating Clock Domain	Length of Event
Peripheral	Event	Description	Event Type	Generating Clock Domain	Length of Event
TCBn	CAPT	CAPT flag set	Pulse	CLK_PER	One CLK_PER period
TCBn	OVF	OVF flag set	Pulse	CLK_PER	One CLK_PER period

The conditions for generating the CAPT and OVF events are identical to those that will raise the corresponding interrupt flags in the Timer/Counter Interrupt Flags (TCBn.INTFLAGS) register. Refer to the EVSYS - Event System section for more details regarding event users and Event System configuration.

The TCB can receive the events described in the following table:

Table 24-4. Event Users and Available Event Actions in TCB
User Name		Description	Input Detection	Async/Sync
Peripheral	Input	Description	Input Detection	Async/Sync
TCBn	CAPT	Time-Out Check Count mode	Edge	Sync
		Input Capture on Event Count mode
		Input Capture Frequency Measurement Count mode
		Input Capture Pulse-Width Measurement Count mode
		Input Capture Frequency and Pulse-Width Measurement Count mode
		Single-Shot Count mode		Both
	COUNT	Event as clock source in combination with a count mode		Sync

CAPT and COUNT are TCB event users that detect and act upon input events.

The COUNT event user is enabled on the peripheral by modifying the Clock Select (CLKSEL) bit field in the Control A (TCBn.CTRLA) register to EVENT and setting up the Event System accordingly.

If the Capture Event Input Enable (CAPTEI) bit in the Event Control (TCBn.EVCTRL) register is written to ‘1’, incoming events will result in an event action as defined by the Event Edge (EDGE) bit in Event Control (TCBn.EVCTRL) register, and the Timer Mode (CNTMODE) bit field in Control B (TCBn.CTRLB) register. The event must last for at least one CLK_PER cycle to be recognized.

If the Asynchronous mode is enabled for Single-Shot mode, the event is edge-triggered and will capture changes on the event input shorter than one peripheral clock cycle.